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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1995 copyright ? intel corporation, 1996 order number: 290219-006 82596dx and 82596sx high-performance 32-bit local area network coprocessor y performs complete csma/cd medium access control (mac) functionse independently of cpu e ieee 802.3 (eoc) frame delimiting y supports industry standard lans e ieee type 10base-t (tpe), ieee type 10base5 (ethernet * ), ieee type 10base2 (cheapernet), ieee type 1base5 (starlan), and the proposed standard type 10base-f e proprietary csma/cd networks up to 20 mb/s y on-chip memory management e automatic buffer chaining e buffer reclamation after receipt of bad frames; optional save bad frames e 32-bit segmented or linear (flat) memory addressing formats y 82586 software compatible y optimized cpu interface e 82596dx bus interface optimized to intel's 32-bit i386 tm dx e 82596sx bus interface optimized to intel's 16-bit i386 tm sx e supports big endian and little endian byte ordering y high-performance 16-/32-bit bus master interface e 66-mb/s bus bandwidth e 33-mhz clock, two clocks per transfer e bus throttle timers e transfers data at 100% of serial bandwidth e 128-byte receive fifo, 64-byte transmit fifo y network management and diagnostics e monitor mode e 32-bit statistical counters y self-test diagnostics y configurable initialization root for data structures y high-speed, 5-v, chmos ** iv technology y 132-pin plastic quad flat pack (pqfp) and pga package (see packaging specifications order number: 240800-001, package type ku and a) i386 tm is a trademark of intel corporation * ethernet is a registered trademark of xerox corporation. ** chmos is a patented process of intel corporation. 290219 1 figure 1. 82596dx/sx block diagram
82596dx/sx 82596dx and 82596sx high-performance 32-bit local area network coprocessor contents page introduction 3 pin descriptions 10 82596 and host cpu interaction 14 82596 bus interface 14 82596 memory addressing 14 82596 system memory structure 16 transmit and receive memory structures 17 transmitting frames 20 receiving frames 21 82596 network management and diagnostics 21 network planning and maintenance 23 station diagnostics and self- test 24 82586 software compatibility 24 initializing the 82596 24 system configuration pointer (scp) 24 writing the sysbus 25 intermediate system configuration pointer (iscp) 26 initialization process 26 controlling the 82596dx/sx 27 82596 cpu access interface (port y ) 27 memory addressing formats 28 little endian and big endian byte ordering 28 command unit (cu) 29 receive unit (ru) 30 system control block (scb) 30 scb offset addresses 33 contents page cbl offset (address) 33 rfa offset (address) 34 scb statistical counters 34 statistical counter operation 34 action commands and operating modes 35 nop 35 individual address setup 36 configure 37 multicast-setup 43 transmit 44 jamming rules 46 tdr 47 dump 49 diagnose 52 receive frame descriptor 52 simplified memory structure 53 flexible memory structure 54 receive buffer descriptor (rbd) 55 pga package thermal specification 60 electrical and timing characteristics 60 absolute maximum ratings 60 dc characteristics 60 ac characteristics 61 82596dx input/output system timings 61 82596sx input/output system timings 63 transmit/receive clock parameters 66 82596dx/sx bus operation 68 system interface a.c. timing characteristics 69 input waveforms 70 serial a.c. timing characteristics 72 outline diagrams 74 revision summary 77 2
82596dx/sx introduction the 82596dx/sx is an intelligent, high-performance 32-bit local area network coprocessor. the 82596dx/sx implements the csma/cd access method and can be configured to support all exist- ing ieee 802.3 standardsetypes 10base-t, 10base5, 10base2, 1base5, and 10broad36. it can also be used to implement the proposed stan- dard type 10base-f. the 82596dx/sx performs high-level commands, command chaining, and inter- processor communications via shared memory, thus relieving the host cpu of many tasks associated with network control. all time-critical functions are performed independently of the cpu, this increases network performance and efficiency. the 82596dx/sx bus interface is optimized for intel's i386 tm dx and i386 tm sx microprocessors. the 82596dx/sx implements all ieee 802.3 medi- um access control and channel interface functions, these include framing, preamble generation and stripping, source address generation, destination ad- dress checking, short-frame detection, and automat- ic length-field handling. data rates up to 20 mb/s are supported. the 82596dx/sx provides a powerful host system interface. it manages memory structures automati- cally, with command chaining and bidirectional data chaining. an on-chip dma controller manages four channels, this allows autonomous transfer of data blocks (buffers and frames) and relieves the cpu of byte transfer overhead. buffers containing errored or collided frames can be automatically recovered with- out cpu intervention. the 82596dx/sx provides an upgrade path for existing 82586 software drivers by providing an 82586-software-compatible mode that supports the current 82586 memory structure. the 82596dx/sx also has a flexible memory structure and a simplified memory structure. the 82596dx/ sx can address up to 4 gigabytes of memory. the 82596dx/sx supports little endian and big endian byte ordering. the 82596dx/sx bus interface is optimized to in- tel's i386 tm dx and i386 sx microprocessors, pro- viding a bus transfer rate of up to 66 mb/s at 33 mhz. the bus interface employs bus throttle tim- ers to regulate 82596dx/sx bus use. two large, in- dependent fifose128 bytes for receive and 64 bytes for transmitetolerate long bus latencies and provide programmable thresholds that allow the user to optimize bus overhead for any worst-case bus latency. the 82596dx/sx provides a wide range of diagnos- tics and network management functions, these in- clude internal and external loopback, exception con- dition tallies, channel activity indicators, optional capture of all frames regardless of destination ad- dress (promiscuous mode), optional capture of er- rored or collided frames, and time domain reflectom- etry for locating fault points on the network cable. the statistical counters, in 32-bit segmented and lin- ear modes, are 32-bits each and include crc errors, alignment errors, overrun errors, resource errors, short frames, and received collisions. the 82596dx/sx also features a monitor mode for net- work analysis. in this mode the 82596dx/sx can capture status bytes, and update statistical coun- ters, of frames monitored on the link without trans- ferring the contents of the frames to memory. this can be done concurrently while transmitting and re- ceiving frames destined for that station. the 82596dx/sx can be used in both baseband and broadband networks. it can be configured for maximum network efficiency (minimum contention overhead) with networks of any length. its highly flexible csma/cd unit supports address field lengths of zero through six bytes for ieee 802.3/ ethernet frame delimitation. it also supports 16- or 32-bit cyclic redundancy checks. the crc can be transferred directly to memory for receive, opera- tions or dynamically inserted for transmit operations. the csma/cd unit can also be configured for full duplex operation for high throughput in point-to-point connections. the 82596 c-step incorporates several new fea- tures not found in previous steppings. the following is a summary of the 82596 c-step's new features. # the 82596 c-step fixes errata found in the a1 and b steppings. # the 82596 c-step has improved ac timings over both the a and b steppings. # the 82596 c-step has a new enhanced big endi- an mode where in linear addressing mode, true 32-bit big endian functionality is achieved. new enhanced big endian mode is enabled by setting bit 7 of the sysbus byte. this mode is software compatible with the big endian mode of the b- step with one exceptioneno 32-bit addresses need to be swapped by software in the c-step. in this new mode, the 82596 c-step treats 32-bit ad- dress pointers as true 32-bit entities and the scb absolute address and statistical counters are still treated as two 16-bit big endian entities. not set- ting this mode will configure the 82596 c-step to be 100% compatible to the a1-step bit endian mode. # the 82596 c-step is hardware and software com- patible to both the a1 and b steppings allowing for easy ``drop-in'' to current designs. pinout and control structures remain unchanged. the 82596dx/sx is fabricated with intel's reliable, 5-v, chmos iv (process 648.8) technology. it is available in a 132-pin pqfp or pga package. 3
82596dx/sx 290219 2 figure 2a. 82596dx pqfp pin configuration 4
82596dx/sx 290219 34 figure 2b. 82596sx pqfp pin configuration 5
82596dx/sx 290219 3 figure 3a. 82596dx pga pin view side 6
82596dx/sx 82596dx pga cross reference by pin name address data control serial n/c v cc v ss interface signal pin no. signal pin no. signal pin no. signal pin no. pin no. pin no. pin no. a 2 n9 d 0 j2 ads m5 cdt a13 k3 b6 a6 a 3 m9 d 1 h3 be0 m7 crs a14 l1 b7 a7 a 4 m10 d 2 g2 be1 p5 cts c11 l2 b10 a8 a 5 p11 d 3 g3 be2 m8 lpbk a12 l3 e2 a10 a 6 n11 d 4 g1 be3 p9 rts c10 n2 e13 c13 a 7 p12 d 5 d1 breq p4 rxc b11 p1 f2 e1 a 8 m11 d 6 c1 bs16 n1 rxd b12 g13 e14 a 9 n12 d 7 f3 ca p3 txc c12 h2 f1 a 10 m12 d 8 d2 clk2 j3 txd a11 h13 g14 a 11 p13 d 9 c2 hlda m6 j13 h1 a 12 l12 d 10 e3 hold p2 k2 h14 a 13 n13 d 11 d3 int/int n3 l13 j1 a 14 m13 d 12 b2 le/be b14 m1 j14 a 15 p14 d 13 b1 lock m4 n6 k1 a 16 k12 d 14 c3 port m2 n7 l14 a 17 n14 d 15 a1 ready m3 n8 n5 a 18 j12 d 16 b3 reset b13 n10 p6 a 19 k13 d 17 c4 w/r n4 p7 a 20 m14 d 18 a2 p8 a 21 h12 d 19 c5 p10 a 22 k14 d 20 a3 a 23 g12 d 21 b4 a 24 f14 d 22 a4 a 25 f12 d 23 c6 a 26 f13 d 24 b5 a 27 d14 d 25 c7 a 28 e12 d 26 a5 a 29 d13 d 27 b8 a 30 d12 d 28 c8 a 31 c14 d 29 a9 d 30 c9 d 31 b9 7
82596dx/sx 290219 35 figure 3b. 82596sx pga pin view side 8
82596dx/sx 82596sx pga cross reference by pin name address data control serial n/c v cc v ss interface signal pin no. signal pin no. signal pin no. signal pin no. pin no. pin no. pin no. a 2 n9 d 0 j2 ads m5 cdt a13 a2 b6 a6 a 3 m9 d 1 h3 ble m7 crs a14 a3 b7 a7 a 4 m10 d 2 g2 bhe p5 cts c11 a4 b10 a8 a 5 p11 d 3 g3 bon p9 lpbk a12 a5 e2 a10 a 6 n11 d 4 g1 breq p4 rts c10 a9 e13 c13 a 7 p12 d 5 d1 ca p3 rxc b11 b3 f2 e1 a 8 m11 d 6 c1 clk2 j3 rxd b12 b4 g13 e14 a 9 n12 d 7 f3 hlda m6 txc c12 b5 h2 f1 a 10 m12 d 8 d2 hold p2 txd a11 b8 h13 g14 a 11 p13 d 9 c2 int/int n3 b9 j13 h1 a 12 l12 d 10 e3 le/be b14 c4 k2 h14 a 13 n13 d 11 d3 lock m4 c5 l13 j1 a 14 m13 d 12 b2 port m2 c6 m1 j14 a 15 p14 d 13 b1 rdy m3 c7 n5 k1 a 16 k12 d 14 c3 reset b13 c8 n6 l14 a 17 n14 d 15 a1 w/r n04 c9 n7 n1 a 18 j12 k3 n8 p6 a 19 k13 l1 n10 p7 a 20 m14 l2 p8 a 21 h12 l3 p10 a 22 k14 n2 a 23 g12 p1 a 24 f14 a 25 f12 a 26 f13 a 27 d14 a 28 e12 a 29 d13 a 30 d12 a 31 c14 9
82596dx/sx pin descriptions symbol pqfp type name and function pin no. clk2 9 i clock. the system clock input provides the fundamental timing for the 82596. it is internally divided by two to generate the 82596 clock. all external timing parameters are specified in reference to the rising edge of clk2. for clock levels see d.c. characteristics. d31d0 1453 i/o data bus. the 32 data bus lines are bidirectional, tri-state lines that provide the general purpose data path between the 82596 and memory. with the 82596dx the bus can be either 16 or 32 bits wide; this is determined by the bs16 signal which is static. the 82596 always drives all 32 data lines during write operations, even with a 16-bit bus. d0 d31 are floated after a reset or when the bus is not acquired. these lines are inputs during a cpu port access; in this mode the cpu writes the next address to the 82596 through the data lines. during port commands (relocatable scp, self-test, and dump) the address must be aligned to a 16 byte boundary. this frees the d 3 d 0 lines so they can be used to distinguish the commands. the following is a summary of the decoding data. d0 d1 d2 d3 d4 d31 function 0000 0000 reset 0100 addr relocatable scp 1000 addr self-test 1100 addr dump command (d15 d0) 14 32 i/o these 16 data bus lines are bidirectional, tri-state lines that provide the entire data path for the 82596sx. in the 82596sx d16 d31 are not connected (nc). a31 a2 70 108 o address lines. these 30 tri-stated address lines output the address bits required for memory operation. these lines are floated after a reset or when the bus is not acquired. a1 112 o the 82596sx requires this additional address line to output the address bits required for memory operation. be3 be0 109 114 o byte enable. (82596dx only.) these tri-stated signals are used to indicate which bytes are involved with the current memory access. the number of byte enable signals asserted indicates the physical size of the data being transferred (1, 2, 3, or 4 bytes). # be0 indicates d0 d7 # be1 indicates d8 d15 # be2 indicates d16 d23 # be3 indicates d24 d31 these lines are floated after a reset or when the bus is not acquired. bhe , ble 113 114 o (82596sx only.) these signals are the byte high enable and byte low enable signals for the 82596sx. bon 109 o bus on. (82596sx only.) this signal is driven high when the 82596 is holding the bus. this signal is tri-stated when the bus is relinquished. bon has the same timing as the byte enables. 10
82596dx/sx pin descriptions (continued) symbol pqfp type name and function pin no. w/r 120 o write/read. this dual-function pin is used to distinguish write and read cycles. this line is floated after a reset or when the bus is not acquired. ads 124 o address status. this tri-state pin is used by the 82596 to indicate that a valid bus cycle has begun and that a31 a2, be3 be0 , and w/r are being driven. it is asserted during t1 bus states. this line is floated after a reset or when the bus is not acquired. rdy 130 i ready. active low. this signal is the acknowledgment from addressed memory that the transfer cycle can be completed. when high, it causes wait states to be inserted. it is ignored at the end of the first clock of the bus cycle's data cycle. this active-low signal does not have an internal pull-up resistor. this signal must meet the setup and hold times to operate correctly. lock 126 o lock. this tri-state pin is used to distinguish locked and unlocked bus cycles. lock generates a semaphore handshake to the cpu. lock can be active for several memory cycles, it goes active during the first locked memory cycle (t1) and goes inactive at the last locked cycle (t2). this line is floated after a reset or when the bus is not acquired. lock can be disabled via the sysbus byte in software. bs16 129 i bus size. this signal allows the 82596dx to work with either 16- or 32-bit bytes. this signal is static and should be tied high for 32-bit operation or low for 16-bit operation. in little endian mode the d0 d15 lines are driven when bs16 is inserted, in big endian mode the d16 d31 lines are driven. hold 123 o hold. the hold signal is active high, the 82596 uses it to request local bus mastership. in normal operation hold goes inactive before hlda. the 82596 can be forced off the bus by deasserting hlda or if the bus throttle timers expire. hlda 118 i hold acknowledge. the hlda signal is active high, it indicates that bus mastership has been given to the 82596. hlda is internally synchronized; after hold is detected low, the cpu drives hlda low. note do not connect hlda to v cc eit will cause a deadlock. a user wanting to give the 82596 permanent access to the bus should connect hlda to hold. if hlda goes inactive before hold, the 82596 will release the bus (by deasserting hold) within a specified number of system clocks. breq 115 i bus request. this signal, when configured to an externally activated mode, is used to trigger the bus throttle timers. 11
82596dx/sx pin descriptions (continued) symbol pqfp type name and function pin no. port 3i port. when this signal is received, the 82596 latches the data on the data bus into an internal 32-bit register. when the cpu is asserting this signal it can write into the 82596 (via the data bus). this pin must be activated twice during all cpu port access commands. reset 69 i reset. this active high, internally synchronized signal causes the 82596 to terminate current activity. the signal must be high for at least five system clock cycles. after five system clock cycles and four txc clock cycles the 82596 will execute a reset when it receives a high reset signal. when reset returns to low, the 82596 waits for the first ca signal and then begins the initialization sequence. le/be 65 i little endian/big endian. this dual-function pin is used to select byte ordering. when le/be is high, little endian byte ordering is used; when low, big endian byte ordering is used for data in frames (bytes) and for control (scb, rfd, cbl, etc.). ca 119 i channel attention. the cpu uses this pin to force the 82596 to begin executing memory resident command blocks. the ca signal is internally synchronized. the signal must be high for at least one system clock. it is latched internally on the high to low edge and then detected by the 82596. the first ca after a reset forces the 82596 into the initialization sequence beginning at location 00fffff6h or an scp address written to the 82596 using cpu port access. all subsequent ca signals cause the 82596 to begin executing new command sequences from the scb. int/int 125 o interrupt. a high signal on this pin notifies the cpu that the 82596 is requesting an interrupt. this signal is an edge triggered interrupt signal, and can be configured to be active high or low. v cc 18 pins (dx) power. a 5v g 10%. 19 pins (sx) v ss 19 pins ground. 0v. (dx and sx) txd 54 o transmit data. this pin transmits data to the serial link. it is high when not transmitting. txc 64 i transmit clock. this signal provides the fundamental timing for the serial subsystem. the clock is also used to transmit data synchronously on the txd pin. for nrz encoding, data is transferred to the txd pin on the high to low clock transition. for manchester encoding, the transmitted bit center is aligned with the low to high transition. transmit clock should always be running for proper device operation. 12
82596dx/sx pin descriptions (continued) symbol pqfp type name and function pin no. lpbk 58 o loopback. this ttl-level control signal enables the loopback mode. in this mode serial data on the txd input is routed through the 82c501 internal circuits and back to the rxd output without driving the transceiver cable. to enable this signal, both internal and external loopback need to be set with the configure command. rxd 60 i receive data. this pin receives nrz serial data only. it must be high when not receiving. rxc 59 i receive clock. this signal provides timing information to the internal shifting logic. for nrz data the state of the rxd pin is sampled on the high to low transition of the clock. rts 57 o request to send. when this signal is low the 82596 informs the external interface that it has data to transmit. it is forced high after a reset or when transmission is stopped. cts 62 i clear to send. an active-low signal that enables the 82596 to send data. it is normally used as an interface handshake to rts . asserting cts high stops transmission. cts is internally synchronized. if cts goes inactive, meeting the setup time to the txc negative edge, the transmission will stop and rts will go inactive within, at most, two txc cycles. crs 63 i carrier sense. this signal is active low, it is used to notify the 82596 that traffic is on the serial link. it is only used if the 82596 is configured for external carrier sense. in this configuration external circuitry is required for detecting traffic on the serial link. crs is internally synchronized. to be accepted, the signal must remain active for at least two serial clock cycles (for crsf e 0). cdt 61 i collision detect. this active-low signal informs the 82596 that a collision has occurred. it is only used if the 82596 is configured for external collision detect. external circuitry is required for collision detection. cdt is internally synchronized. to be accepted, the signal must remain active for at least two serial clock cycles (for cdtf e 0). 13
82596dx/sx 82596 and host cpu interaction the 82596dx/sx and the host cpu communicate through shared memory. because of its on-chip dma capability, the 82596 can make data block transfers (buffers and frames) independently of the cpu; this greatly reduces the cpu byte transfer overhead. note: the 82596dx and 82596sx differ in their address pin definitions and their data bus sizes. information in this data sheet applies to both versions unless otherwise stated. the 82596 is a multitasking coprocessor that com- prises two independent logical unitsethe command unit (cu) and the receive unit (ru). the cu exe- cutes commands from shared memory. the ru han- dles all activities related to frame reception. the in- dependence of the cu and ru enables the 82596 to engage in both activities simultaneouslyethe cu can fetch and execute commands from memory while the ru is storing received frames in memory. the cpu is only involved with this process after the cu has executed a sequence of commands or the ru has finished storing a sequence of frames. the cpu and the 82596 use the hardware signals interrupt (int) and channel attention (ca) to initiate communication with the system control block (scb), see figure 4. the 82596 uses int to alert the cpu of a change in the contents of the scb, the cpu uses ca to alert the 82596. the 82596 has a cpu port access state that allows the cpu to execute certain functions without ac- cessing memory. the 82596 port pin and data bus pins are used to enable this feature. the cpu can directly activate four operations when the 82596 is in this state. # write an alternative system configuration pointer (scp). this can be used when the 82596 cannot use the default scp address space. # write a different dump command pointer and ex- ecute dump. this can be used for troubleshoot- ing no response problems. # the cpu can reset the 82596 via software with- out disturbing the rest of the system. # a self-test can be used for board testing; the 82596 will execute a self-test and write the re- sults to memory. 82596 bus interface the 82596dx/sx has bus interface timings and pin definitions that are compatible with intel's 32-bit i386 dx and i386 sx microprocessors. this eliminates the need for additional bus interface logic. operating at 33 mhz, the 82596's bus bandwidth can be as high as 66 mb/s. since ethernet only requires 1.25 mb/s, this leaves a considerable amount of bandwidth for the cpu. the 82596 also has a bus throttle to regulate its use of the bus. two timers can be programmed through the scb: one controls the maximum time the 82596 can remain on the bus, the other controls the time the 82596 must stay off the bus (see figure 5). the bus throttle can be pro- grammed to trigger internally with hlda or external- ly with breq. these timers can restrict the 82596 hold activation time and improve bus utilization. 82596 memory addressing the 82596 has a 32-bit memory address range, which allows addressing up to four gigabytes of memory. the 82596 has three memory addressing modes (see table 1). # 82586 mode. the 82596 has a 24-bit memory address range. the system control block, com- mand list, receive descriptor list, and buffer descriptors must reside in one 64-kb memory segment. transmit and receive buffers can re- side in a 24-bit address space. # 32-bit segmented mode. the 82596 has a 32- bit memory address range. the system control block, command list, receive descriptor list, and buffer descriptors must reside in one 64-kb memory segment. transmit and receive buffers can reside in a 32-bit address space. # linear mode. the 82596 has a 32-bit memory address range. any memory structure can reside anywhere within the 32-bit memory address range. 14
82596dx/sx 290219 4 figure 4. 82596 and host cpu intervention 290219 5 figure 5. bus throttle timers table 1. 82596 memory addressing formats operation mode pointer or offset 82586 32-bit linear segmented iscp address 24-bit linear 32-bit linear 32-bit linear scb address base (24) a offset (16) base (32) a offset (16) 32-bit linear command block pointers base (24) a offset (16) base (32) a offset (16) 32-bit linear rx frame descriptors base (24) a offset (16) base (32) a offset (16) 32-bit linear tx frame descriptors base (24) a offset (16) base (32) a offset (16) 32-bit linear rx buffer descriptors base (24) a offset (16) base (32) a offset (16) 32-bit linear tx buffer descriptors base (24) a offset (16) base (32) a offset (16) 32-bit linear rx buffers 24-bit linear 32-bit linear 32-bit linear tx buffers 24-bit linear 32-bit linear 32-bit linear 15
82596dx/sx 290219 6 figure 6. 82596 shared memory structure 82596 system memory structure the shared memory structure consists of four parts: the initialization root, the system control block, the command list, and the receive frame area (see figure 6). the initialization root is in an established location known to the host cpu and the 82596 (00fffff6h). however, the cpu can establish the initialization root in another location by using the cpu port ac- cess. this root is accessed during initialization, and points to the system control block. the system control block serves as a bidirectional mail drop for the host cpu and the 82596 cu and ru. it is the central point through which the cpu and the 82596 exchange control and status information. the scb has two areas. the first contains instruc- tions from the cpu to the 82596. these include: control of the cu and ru (start, abort, suspend, and resume), a pointer to the list of cu commands, a pointer to the receive frame area, a set of inter- rupt acknowledge bits, and the t-on and t-off timers for the bus throttle. the second area contains status information the 82596 is sending to the cpu. such as, the cu and ru states (idle, active 16
82596dx/sx ready, suspended, no receive resources, etc.), in- terrupt bits (command completed, frame received, cu not ready, and ru not ready), and statistical counters. the command list functions as a program for the cu; individual commands are placed in memory units called command blocks (cbs). these cbs contain the parameters and status of specific high- level commands called action commands; e.g., transmit or configure. transmit causes the 82596 to transmit a frame. the transmit cb contains the destination address, the length field, and a pointer to a list of linked buffers holding the frame that is to be constructed from sev- eral buffers scattered throughout memory. the command unit operates without cpu intervention; the dma for each buffer, and the prefetching of ref- erences to new buffers, is performed in parallel. the cpu is notified only after a transmission is complete. the receive frame area is a list of free frame de- scriptors (descriptors not yet used) and a list of user- prepared buffers. frames arrive at the 82596 unso- licited; the 82596 must always be ready to receive and store them in the free frame area. the re- ceive unit fills the buffers when it receives frames, and reformats the free buffer list into received- frame structures. the frame structure is, for all prac- tical purposes, identical to the format of the frame to be transmitted. the first frame descriptor is refer- enced by the scb. unless the 82596 is configured to save bad frames, the frame descriptor, and the associated buffer descriptor, which is wasted when a bad frame is received, are automatically reclaimed and returned to the free buffer list. receive buffer chaining (storing incoming frames in a linked buffer list) significantly improves memory utilization. without buffer chaining, the user must al- locate consecutive blocks of memory, each capable of containing a maximum frame (for ethernet, 1518 bytes). since an average frame is about 200 bytes, this is very inefficient. with buffer chaining, the user can allocate small buffers and the 82596 will only use those that are needed. figure 7 a d illustrates how the 82596 uses the receive frame area. figure 7a shows an unused receive frame area composed of free frame de- scriptors and free receive buffers prepared by the user. the scb points to the first frame descriptor of the frame descriptor list. figure 7b shows the same receive frame area after receiving one frame. this first frame occupies two receive buffers and one frame descriptorea valid received frame will only occupy one frame descriptor. after receiv- ing this frame the 82596 sets the next free frame descriptor rbd pointer to the next free rbd. figure 7c shows the rfa after receiving a second frame. in this example the second frame occupies only one receive buffer and one rfd. the 82596 again sets the rbd pointer. this process is repeated again in figure 7d, showing the reception of another frame using one receive buffer; in this example there is an extra frame descriptor. transmit and receive memory structures there are three memory structures for reception and transmission. the 82586 memory structure, the flexible memory structure, and the simplified memo- ry structure. the 82586 mode is selected by config- uring the 82596 during initialization. in this mode all the 82596 memory structures are compatible with the 82586 memory structures. when the 82596 is not configured to the 82586 mode, the other two memory structures, simplified and flexible, are available for transmitting and re- ceiving. these structures are selected by setting the s/f bit in the transmit command and/or the re- ceive frame descriptor (see figures 29, 30, 41, and 42). it is recommended that any linked list of buffers be relegated to a single typeeeither simplified or flexible. the simplified memory structure offers a simple structure for ease of programming (see fig- ure 8). all information about a frame is contained in one structure; for example, during reception the rfd and data field are contained in one structure. the flexible memory structure (see figure 9) has a control field that allows the programmer to specify the amount of receive data the rfd will contain for receive operations and the amount of transmit data the transmit command block will contain for trans- mit operations. for example, when the control field in the rfd is set to 20 bytes during a reception, the first 20 bytes of the data field are stored in the rfd (6 bytes of destination address, 6 bytes of source address, 2 bytes of length field, and 6 bytes of data), and the remainder of the data field is stored in the receive data buffers. this is useful for capturing frame headers when header information is con- tained in the data field. the header information can then be automatically stored in the rfd partitioned from the receive data buffer. the control field can also be used for the transmit command when the flexible memory structure is used. the quantity of data field bytes to be transmit- ted from the transmit command block is specified by the variable control field. 17
82596dx/sx 290219 7 figure 7. frame reception in the rfa 18
82596dx/sx 290219 8 figure 8. simplified memory structure 290219 9 figure 9. flexible memory structure 19
82596dx/sx transmitting frames the 82596 executes high-level action commands from the command list in system memory. action commands are fetched and executed in parallel with the host cpu operation, thereby significantly improv- ing system performance. the format of the action commands is shown in figure 10. figure 28 shows the 82586 mode, and figures 29 and 30 shows the command formats of the linear and 32-bit segment- ed modes. a single transmit command contains, as part of the command-specific parameters, the destination ad- dress and length field of the transmitted frame and a pointer to buffer area in memory containing the data portion of the frame. the data field is contained in a memory data structure consisting of a buffer de- scriptor (bd) and a data buffereor a linked list of buffer descriptors and bufferseas shown in figure 11. multiple data buffers can be chained together using the bds. thus, a frame with a long data field can be transmitted using several (shorter) data buffers chained together. this chaining technique allows the system designer to develop efficient buffer manage- ment. the 82596 automatically generates the preamble (alternating 1s and 0s) and start frame delimiter, fetches the destination address and length field from the transmit command, inserts its unique address as the source address, fetches the data field speci- fied by the transmit command, and computes and appends the crc to the end of the frame (see fig- ure 12). in the linear and 32-bit segmented mode the crc can be optionally inserted on a frame-by- frame basis by setting the nc bit in the transmit command block (see figures 29 and 30). the 82596 generates the standard end of carrier (eoc) start and end frame delimiters. in eoc, the start frame delimiter is 10101011 and the end frame delimiter is indicated by the lack of a signal after the last bit of the frame check sequence field has been transmitted. in eoc, the 82596 can be configured to extend short frames by adding pad bytes (7eh) dur- ing transmission, according to the length field. when a collision occurs, the 82596 manages the jam, random wait, and retry processes, reinitializing dma pointers without cpu intervention. multiple frames can be sent by linking the appropriate num- ber of transmit commands together. this is particu- larly useful when transmitting a message larger than the maximum frame size (1518 bytes for ethernet). 290219 10 figure 10. action command format 290219 11 figure 11. data buffer descriptor and data buffer structure 20
82596dx/sx start destination source length data frame end preamble frame address address field field check frame delimiter sequence delimiter figure 12. frame format receiving frames to reduce cpu overhead, the 82596 is designed to receive frames without cpu supervision. the host cpu first sets aside an adequate receive buffer space and then enables the 82596 receive unit. once enabled, the ru watches for arriving frames and automatically stores them in the receive frame area (rfa). the rfa contains receive frame de- scriptors, receive buffer descriptors, and data buff- ers (see figure 13). the individual receive frame descriptors make up a receive descriptor list (rdl) used by the 82596 to store the destination and source addresses, the length field, and the status of each frame received (see figure 14). once enabled, the 82596 checks each passing frame for an address match. the 82596 will recog- nize its own unique address, one or more multicast addresses, or the broadcast address. if a match is found the 82596 stores the destination and source addresses and the length field in the next available rfd. it then begins filling the next available data buffer on the fbl, which is pointed to by the current rfd, with the data portion of the incoming frame. as one data buffer is filled, the 82596 automatically fetches the next db on the fbl until the entire frame is received. this buffer chaining technique is particu- larly memory efficient because it allows the system designer to set aside buffers to fit frames much shorter than the maximum allowable frame length. if al-loc e 1, or if the flexible memory structure is used, the addresses and length field can be placed in the receive buffer. once the entire frame is received without error, the 82596 does the following housekeeping tasks. # the actual count field of the last buffer descrip- tor used to hold the frame just received is updat- ed with the number of bytes stored in the associ- ated data buffer. # the next available receive frame descriptor is fetched. # the address of the next available buffer descrip- tor is written to the next available receive frame descriptor. # a frame received interrupt status bit is posted in the scb. # an interrupt is sent to the cpu. if a frame error occurs, for example a crc error, the 82596 automatically reinitializes its dma pointers and reclaims any data buffers containing the bad frame. the 82596 will continue to receive frames without cpu help as long as receive frame de- scriptors and data buffers are available. 82596 network management and diagnostics the behavior of data communication networks is normally very complex because of their distributed and asynchronous nature. it is particularly difficult to pinpoint a failure when it occurs. the 82596 has ex- tensive diagnostic and network management func- tions that help improve reliability and testability. the 82596 reports on the following events after each frame is transmitted. # transmission successful. # transmission unsuccessful. lost carrier sense. # transmission unsuccessful. lost clear to send. # transmission unsuccessful. a dma underrun oc- curred because the system bus did not keep up with the transmission. # transmission unsuccessful. the number of colli- sions exceeded the maximum allowed. # number of collisions. the number of collisions experienced during transmission of the frame. # heartbeat indicator. this indicates the presence of a heartbeat during the last interframe spacing (ifs) after transmission. when configured to save bad frames the 82596 checks each incoming frame and reports the follow- ing errors. # crc error. incorrect crc in a properly aligned frame. # alignment error. incorrect crc in a misaligned frame. # frame too short. the frame is shorter than the value configured for minimum frame length. # overrun. part of the frame was not placed in memory because the system bus did not keep up with incoming data. # out of buffer. part of the frame was discarded because of insufficient memory storage space. # receive collision. a collision was detected during reception and the destination address of the in- coming frame passes 82596 address filtering. collisions in the preamble are not counted. # length error. a frame not matching the frame length parameter was detected. 21
82596dx/sx 290219 12 figure 13. receive frame area diagram 290219 13 figure 14. receive frame descriptor 22
82596dx/sx network planning and maintenance to properly plan, operate, and maintain a communi- cation network, the network management entity must accumulate information on network behavior. the 82596 provides a rich set of network-wide diag- nostics that can serve as the basis for a network management entity. information on network activity is provided in the status of each frame transmitted. the 82596 reports the following activity indicators after each frame. # number of collisions. the number of collisions the 82596 experienced while attempting to trans- mit the frame. # deferred transmission. during the first transmis- sion attempt the 82596 had to defer to traffic on the link. the 82596 updates its 32-bit statistical counters af- ter each received frame that both passes address filtering and is longer than the minimum frame length configuration parameter. the 82596 reports the following statistics. # crc errors. the number of well-aligned frames that experienced a crc error. # alignment errors. the number of misaligned frames that experienced a crc error. # no resources. the number of frames that were discarded because of insufficient resources for reception. # overrun errors. the number of frames that were not completely stored in memory because the system bus did not keep up with incoming data. # receive collision counter. the number of colli- sions detected during receive. collisions occur- ring before the minimum frame length will be counted as short frames. collisions in the pream- ble will not be counted at all. # short frame counter. the number of frames that were discarded because they were shorter than the configured minimum frame length. once again, these counters are not updated until the 82596 decodes a destination address match. the 82596 can be configured to promiscuous mode. in this mode it captures all frames transmitted on the network without checking the destination address. this is useful when implementing a monitoring sta- tion to capture all frames for analysis. a useful method of capturing frame headers is to use the simplified memory mode, configure the 82596 to save bad frames, and configure the 82596 to promiscuous mode with space in the rfd allocated for specific number of receive data bytes. the 82596 will receive all frames and put them in the rfd. frames that exceed the available space in the rfd will be truncated, the status will be updated, and the 82596 will retrieve the next rfd. this allows the user to capture the initial data bytes of each frame (for instance, the header) and discard the re- mainder of the frame. the 82596 also has a monitor mode for network analysis. during normal operation the receive func- tion enables the 82596 to receive frames which pass address filtering. these frames must have the start of frame delimiter (sfd) field and must be longer than the absolute minimum frame length of 5 bytes (6 bytes in case of multicast address filtering). con- tents and status of the received frames are trans- ferred to memory. the monitor function enables the 82596 to simply evaluate the incoming frames. the 82596 can monitor the frames that pass or do not pass the address filtering. it can also monitor frames which do not have the sfd fields. the 82596 can be configured to only keep statistical information about monitor frames. three options are available in the monitor mode. these modes are selectable by the two monitor mode configuration bits available in the configuration command. when the first option is selected, the 82596 receives good frames that pass address filtering and trans- fers them to memory while monitoring frames that do not pass address filtering or are shorter than the minimum frame size (these frames are not trans- ferred to memory). when this option is used the 82596 updates six counters: crc errors, alignment errors, no resource errors, overrun errors, short frames, and total good frames received. when the second option is selected, the receive function is completely disabled. the 82596 monitors only those frames that pass address filterings and meet the minimum frame length requirement. when this option is used the 82596 updates six counters: crc errors, alignment errors, total frames (good and bad), short frames, collisions detected, and total good frames. when the third option is selected, the receive func- tion is completely disabled. the 82596 monitors all frames, including frames that do not have a start frame delimiter. when this option is used the 82596 updates six counter (crc errors, alignment errors, total frames (good and bad), short frames, collisions detected, and total good frames. 23
82596dx/sx station diagnostics and self-test the 82596 provides a large set of diagnostic and network management functions. these include inter- nal and external loopback and time domain reflec- tometry for locating fault points in the network cable. the 82596 ensures software reliability by dumping the contents of the 82596 internal registers into sys- tem memory. the 82596 has a self-test mode that enables it to run an internal self-test and place the results in system memory. 82586 software compatibility the 82596 has a software-compatible state in which all its memory structures are compatible with the 82586 memory structure. this includes all the action commands, the receive frame area (including the rfd, buffer descriptors, and data buffers), the sys- tem control block, and the initialization procedures. there are two minor differences between the 82596 in the 82586-compatible memory structure and the 82586. # when the internal and external loopback bits in the configure command are set to 11 the 82596 is in external loopback and the lpbk pin is acti- vated; in the 82586 this situation would produce internal loopback. # during a dump command both the 82596 and 82586 dump the same number of bytes; however, the data format is different. initializing the 82596 a reset command is issued to the 82596 to prepare it for normal operation. the 82596 is initialized through two data structures that are addressed by two pointers, the system configuration pointer (scp) and the intermediate system configuration pointer (iscp). the initialization procedure begins when a channel attention signal is asserted after reset. the 82596 uses the address of the double word that contains the scp as a defaulte 00fffff4h. before the ca signal is asserted this default address can be changed to any other avail- able address by asserting the port pin and provid- ing the desired address over the d 31 d 4 pins of the address bus. pins d 3 d 0 must be 0010; i.e., any alternative address must be aligned to 16 byte boundaries. all addresses sent to the 82596 must be word aligned, which means that all pointers and memory structures must start on an even address (a 0 e zero). system configuration pointer (scp) the scp contains the sysbus byte and the loca- tion of the next structure of the initialization process, the iscp. the following parameters are selected in the sysbus. # the 82596 operation mode. # the bus throttle timer triggering method. # lock enabled. # interrupt polarity. # big endian 32-bit entity mode. byte ordering is determined by the le/be pin. le/be e 1 selects little endian byte ordering and le/be e 0 selects big endian byte ordering. note: in the following, x indicates a bit not checked in 82586 mode. this bit must be set to 0 in all other modes. 24
82596dx/sx the following diagram illustrates the format of the scp. 31 16 odd word 15 0 even word xxxxxxxx sysbus 0000000000000000 0fffff4h xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0fffff8h a31a24 a23 a0 iscp address 0fffffch a31a24 are not checked in 82586 mode. xx areas are not checked in 82586 mode; they must be 0 in all other modes. 290219 14 iscp addresse the physical address of the iscp. in the 82586 mode, bits a31 a24 are considered to be zero. figure 15. the system configuration pointer writing the sysbus when writing the sysbus byte it is important to pay attention to the byte order. # when a little endian processor is used, the sysbus byte is located at byte address 00fffff6h (or address n a 2 if an alternative scp address n was programmed). # when a processor using big endian byte ordering is used, the sysbus, alternative scp, and iscp ad- dresses will be different. # the sysbus byte is located at 00fffff7h. # if an alternative scp address is programmed, the sysbus byte should be at byte address n a 1. 25
82596dx/sx intermediate system configuration pointer (iscp) the iscp indicates the location of the system control block. often the scp is in rom and the iscp is in ram. the cpu loads the scb address (or an equivalent data structure) into the iscp and asserts ca. this channel attention signal causes the 82596 to begin its initialization procedure and to get the scb address from the iscp and scp. in 82586 and 32-bit segmented modes the scp base address is also the base address of all command blocks, frame descriptors, and buffer descriptors (but not buffers). all these data structures must reside in one 64-kb segment; however, in linear mode no such limitation is imposed. the following diagram illustrates the iscp format. odd word even word 31 16 15 8 7 0 a15 a0 scb offset busy iscp a23 a0 scb base address iscp a 4 u x x x x x x x x e in 82586 mode a31 a24 e in 32-bit segmented mode busy e indicates that the 82596 is being initialized. the cpu sets the iscp to 01h before it gives the first ca to the 82596. the iscp is cleared by the 82596 after the scb base and offset are read. note that the most significant byte of the first word of the iscp is not modified when busy is cleared. scb offsete this 16-bit quantity specifies the offset portion of the address of the scb. scb base e specifies the base portion of the address of the scb. the base of scb is also the base of all 82596 command blocks, frame descriptors and buffer descriptors. in the 82586 mode, bits a31 a24 are considered to be zero. figure 16. the intermediate system configuration pointere82586 and 32-bit segmented modes odd word even word 31 16 15 8 7 0 0 0 0 0 0 0 busy iscp a31 a0 scb absolute address iscp a 4 busy e indicates that the 82596 is being initialized. the iscp is set to 01h by the cpu before its first ca to the 82596. it is cleared by the 82596 after the scb address is read. scb addresse this 32-bit quantity specifies the physical address of the scb. figure 17. the intermediate system configuration pointerelinear mode. initialization process the cpu sets up the scp, iscp, and the scb structures, and, if desired, an alternative scp address. it also sets busy to 01h. the 82596 is initialized when a channel attention signal follows a reset signal, causing the 82596 to access the system configuration pointer. the sysbus byte, the operational mode, the bus throttle timer triggering method, the interrupt polarity, and the state of lock are read. after reset the bus throttle 26
82596dx/sx timers are essentially disabledethe t-on value is infinite, the t-off value is zero. after the scp is read, the 82596 reads the iscp and saves the scb address. in 82586 and 32-bit segmented modes this address is represented as a base address plus the offset (this base address is also the base address of all the control blocks). in linear mode the base address is also an absolute address. the 82596 clears busy, sets cx and cnr to equal 1 in the scb, clears the scb command word, sends an interrupt to the cpu, and awaits another channel attention signal. reset configures the 82596 to its default state before ca is asserted. controlling the 82596dx/sx the host cpu controls the 82596 with the commands, data structures, and methods described in this section. the cpu and the 82596 communicate through shared memory structures. the 82596 contains two indepen- dent units: the command unit and the receive unit. the command unit executes commands from the cpu, and the receive unit handles frame reception. these two units are controlled and monitored by the cpu through a shared memory structure called the system control block (scb). the cpu and the 82596 use the ca and int signals to communicate with the scb. 82596 cpu access interface (port ) the 82596 has a cpu access interface that allows the host cpu to do four things. # write an alternative system configuration pointer address. # write an alternative dump area pointer and perform dump. # execute a software reset. # execute a self-test. the following events initiate the cpu access state. # presence of an address on the d 31 d 4 data bus pins. # the d 3 d 0 pins are used to select one of the four functions. # the port input pin is asserted, as in a regular write cycle. note the scp dump and self-test addresses must be 16-byte aligned. the 82596 requires two 16-bit write cycles for a port command. the first write holds the internal machines and reads the first 16 bits, the second activates the port command and reads the second 16 bits. the port reset is useful when only the 82596 needs to be reset. the cpu must wait for 10-system and 5-se- rial clocks before issuing another ca to the 82596; this new ca begins a new initialization process. the dump function is useful for troubleshooting no response problems. if the chip is in a no response state, the port dump operation can be executed and a port reset can be used to reinitialize the 82596 without disturbing the rest of the system. the self-test function can be used for board testing; the 82596 will execute a self-test and write the results to memory. table 2. port function selection d 31 d 4 d 0 function addresses and results d 3 d 2 d 1 d 0 reset a31 don't care a4 0 0 0 0 self-test a31 self-test results address a4 0 0 0 1 scp a31 alternative scp address a4 0 0 1 0 dump a31 dump area pointer a4 0 0 1 1 27
82596dx/sx memory addressing formats the 82596 accesses memory by 32-bit addresses. there are two types of 32-bit addresses: linear and seg- mented. the type of address used depends on the 82596 operating mode and the type of memory structure it is addressing. the 82596 has three operating modes. # 82586 mode # a linear address is a single 24-bit entity. address pins a 31 a 24 are always zero. # a segmented address uses a 24-bit base and a 16-bit offset. # 32-bit segmented mode # a linear address is a single 32-bit entity. # a segmented address uses a 32-bit base and a 16-bit offset. note: in the previous two memory addressing modes, each command header (cb, tbd, rfd, rbd, and scb) must wholly reside within one segment. if the 82596 encounters a memory structure that does not follow this restriction, the 82596 will fetch the next contiguous location in memory (beyond the segment). # linear mode # a linear address is a single 32-bit entity. # there are no segmented addresses. linear addresses are primarily used to address transmit and receive data buffers. in the 82586 and 32-bit segmented modes, segmented addresses (base plus offset) are used for all command blocks, buffer descrip- tors, frame descriptors, and system control blocks. when using segmented addresses, only the offset portion of the entity being addressed is specified in the block. the base for all offsets is the sameethat of the scb. see table a. little endian and big endian byte ordering the 82596 supports both little endian and big endian byte ordering for its memory structures. the 82596a1 stepping supports big endian byte ordering for word and byte entities. dword entities are not supported with 82596a1 big endian byte ordering. this results in slightly different 82596 memory structures for big endian operation. these structures are defined in the 32-bit lan components a1 manual. 28
82596dx/sx the 82596 b stepping supports big endian byte ordering for dword, word, and byte entities in linear mode only. all 82596 b 32-bit address pointers are treated as 32-bit big endian entities, however, the scb absolute address and statistical counters are treated as two 16-bit big endian entities. this 32-bit big endian entity support is configured via bit 7 in the sysbus byte. the 82596 c-step has a new enhanced big endian mode where in linear addressing mode, true 32-bit big endian functionality is achieved. new enhanced big endian mode is enabled exactly the same as the b-step, by setting bit 7 of the sysbus byte. this mode is software compatible with the big endian mode of the b-step with one exceptioneno 32-bit addresses need to be swapped by software in the c-step. in this new mode, the 82596 c-step treats 32-bit address pointers as true 32-bit entities and the scb absolute address and statistical counters are still treated as two 16-bit big endian entities. not setting this mode will configure the 82596 c-step to be 100% compatible to the a1-step big endian mode. note: all 82596 memory entities must be word or dword aligned, except the transmit buffers can be byte aligned for the 82596 b or c steppings. an example of a double word entity is a frame descriptor command/status dword, whereas the raw data of the frame are byte entities. both 32- and 16-bit buses are supported. when a 16-bit bus is used with big endian memory organization, data lines d 15 d 0 are used. the 82596 has an internal crossover that handles these swap operations. command unit (cu) the command unit is the logical unit that executes action commands from a list of commands very similar to a cpu program. a command block is associated with each action command. the cu is modeled as a logical machine that takes, at any given time, one of the following states. # idle. the cu is not executing a command and is not associated with a cb on the list. this is the initial state. # suspended. the cu is not executing a command; however, it is associated with a cb on the list. the suspend state can only be reached if the cpu forces it through the scb or sets the suspend bit in the rfd. # active. the cu is executing an action command and pointing to its cb. the cpu can affect cu operation in two ways: by issuing a cu control command or by setting bits in the command word of the action command. when programming the 82596 cu, it is important to consider the asynchronous way the 82596 processes commands. if a command is issued to the 82596 cu, it may be busy processing other commands. in order to avoid asynchronous race conditions, the following guidelines are recommended to the 82596 programmer: # if the cu is already in the active state, and another command needs to be executed, it is unwise to immediately issue another cu start command. if a new command (or list of commands) needs to be started, first issue a cu suspend command, wait for the cu to become suspended, then issue the new cu start. this will insure that all commands are processed correctly. # in general, it is a good idea to make sure any cu command has been accepted and executed before issuing a new control command to the cu. 29
82596dx/sx receive unit (ru) the receive unit is the logical unit that receives frames and stores them in memory. the ru is modeled as a logical machine that takes, at any given time, one of the following states. # idle. the ru has no memory resources and is discarding incoming frames. this is the initial state. # no resources. the ru has no memory resources and is discarding incoming frames. this state differs from idle in that the ru accumulates statistics on the number of discarded frames. # suspended. the ru has memory available for storing frames, but is discarding them. the suspend state can only be reached if the cpu forces it through the scb or sets the suspend bit in the rfd. # ready. the ru has memory available and is storing incoming frames. the cpu can affect ru operation in three ways: by issuing a ru control command, by setting bits in the frame descriptor command word of the frame being received, or by setting the el bit of the current buffer's buffer descriptor. when programming the 82596 ru, it is important to consider the asynchronous way the 82596 processes receive frames. if an ru start is issued to the 82596 ru, it may be busy processing other incoming packets. in order to avoid asynchronous race conditions, the following guidelines are recommended to the 82596 pro- grammer: # if the ru is already in the ready state, and a new rfa is required to be started, it is unwise to immediately issue another ru start command. if the new rfa needs to be started, first issue an ru suspend com- mand, wait for the ru to become suspended, then issue the new ru start. this will insure that all incoming frames are received correctly. # in general, it is a good idea to make sure any ru command has been accepted and executed before issuing a new control command to the ru. system control block (scb) the scb is a memory block that plays a major role in communications between the cpu and the 82596. such communications include the following. # commands issued by the cpu # status reported by the 82596 control commands are sent to the 82596 by writing them into the scb and then asserting ca. the 82596 examines the command, performs the required action, and then clears the scb command word. control commands perform the following types of tasks. # operation of the command unit (cu). the scb controls the cu by specifying the address of the command block list (cbl) and by starting, suspending, resuming, or aborting execution of cbl commands. 30
82596dx/sx # operation of the bus throttle. the scb controls the bus throttle timers by providing them with new values and sending the load and start timer commands. the timers can be operated in both the 32-bit segmented and linear modes. # reception of frames by the receive unit (ru). the scb controls the ru by specifying the address of the receive frame area and by starting, suspending, resuming, or aborting frame reception. # acknowledgment of events that cause interrupts. # resetting the chip. the 82596 sends status reports to the cpu via the system control block. the scb contains four types of status reports. # the cause of the current interrupts. these interrupts are caused by one or more of the following 82596 events. # the command unit completes an action command that has its i bit set. # the receive unit receives a frame. # the command unit becomes inactive. # the receive unit becomes not ready. # the status of the command unit. # the status of the receive unit. # status reports from the 82596 regarding reception of corrupted frames. events can be cleared only by cpu acknowledgment. if some events are not acknowledged by the ack field the interrupt signal (int) will be reissued after channel attention (ca) is processed. furthermore, if a new event occurs while an interrupt is set, the interrupt is temporarily cleared to trigger edge-triggered interrupt controllers. the cpu uses the channel attention line to cause the 82596 to examine the scb. this signal is trailing-edge triggeredethe 82596 latches ca on the trailing edge. the latch is cleared by the 82596 before the scb control command is read. 31 16 odd word 15 0 even word ack x cuc r ruc x x x x stat 0 cus 0 rus 0000scb rfa offset cbl offset scb a 4 alignment errors crc errors scb a 8 overrun errors resource errors scb a 12 figure 18. scbe82586 mode 31 16 odd word 15 0 even word ack 0 cuc r ruc 0 0 0 0 stat 0 cus rus t 0 0 0 scb rfa offset cbl offset scb a 4 crc errors scb a 8 alignment errors scb a 12 resource errors ( * ) scb a 16 overrun errors ( * ) scb a 20 rcvcdt errors ( * ) scb a 24 short frame errors scb a 28 t-on timer t-off timer scb a 32 * in monitor mode these counters change function figure 19. scbe32-bit segmented mode 31
82596dx/sx 31 16 odd word 15 0 even word ack 0 cuc r ruc 0 0 0 0 stat 0 cus rus t 0 0 0 scb command block address scb a 4 receive frame area address scb a 8 crc errors scb a 12 alignment errors scb a 16 resource errors ( * ) scb a 20 overrun errors ( * ) scb a 24 rcvcdt errors ( * ) scb a 28 short frame errors scb a 32 t-on timer t-off timer scb a 36 * in monitor mode these counters change function figure 20. scbelinear mode command word 31 16 ack 0 cuc r ruc 0 0 0 0 scb a 2 these bits specifiy the action to be performed as a result of a ca. this word is set by the cpu and cleared by the 82596. defined bits are: bit 31 ack-cx e acknowledges that the cu completed an action command. bit 30 ack-fr e acknowledges that the ru received a frame. bit 29 ack-cna e acknowledges that the command unit became not active. bit 28 ack-rnr e acknowledges that the receive unit became not ready. bits 24 26 cuc e (3 bits) this field contains the command to the command unit. valid values are: 0 e nop (does not affect current state of the unit). 1 e start execution of the first command on the cbl. if a command is executing, complete it before starting the new cbl. the beginning of the cbl is in cbl offset (address). 2 e resume the operation of the command unit by executing the next command. this operation assumes that the command unit has been previously sus- pended. 3 e suspend execution of commands on cbl after current command is complete. 4 e abort current command immediately. 5 e loads the bus throttle timers so they will be initialized with their new values after the active timer (t-on or t-off) reaches terminal count. if no timer is active new values will be loaded immediately. this command is not valid in 82586 mode. 6 e loads and immediately restarts the bus throttle timers with their new values. this command is not valid in 82586 mode. 7 e reserved. 32
82596dx/sx bits 20 22 ruc e (3 bits) this field contains the command to the receive unit. valid values are: 0 e nop (does not alter current state of unit). 1 e start reception of frames. the beginning of the rfa is contained in the rfa offset (address). if a frame is being received complete reception before starting. 2 e resume frame reception (only when in suspended state). 3 e suspend frame reception. if a frame is being received complete its reception before suspending. 4 e abort receiver operation immediately. 5 7 e reserved. bit 23 reset e reset chip (logically the same as hardware reset). status word 15 0 stat 0 cus 0 rus 0 0 0 0 scb 82586 mode 15 0 stat 0 cus rus t 0 0 0 scb 32-bit segmented and linear modes indicates the status of the 82596. this word is modified only by the 82596. defined bits are: bit 15 cx e the cu finished executing a command with its i (interrupt) bit set. bit 14 fr e the ru finished receiving a frame. bit 13 cna e the command unit left the active state. bit 12 rnr e the receive unit left the ready state. bits 8 10 cus e (3 bits) this field contains the status of the command unit. valid values are: 0 e idle 1 e suspended 2 e active 3 7 e not used bits 4 7 rus e this field contains the status of the receive unit. valid values are: 0h (0000) e idle 1h (0001) e suspended 2h (0010) e no resources. this bit indicates both no resources due to lack of rfds in the rdl and no resources due to lack of rbds in the fbl. 4h (0100) e ready ah (1010) e no resources due to no more rbds. (not in the 82586 mode.) ch (1100) e no more rbds (not in the 82586 mode). no other combinations are allowed. bit 3 t e bus throttle timers loaded (not in 82586 mode). scb offset addresses cbl offset (address) in 82586 and 32-bit segmented modes this 16-bit quantity indicates the offset portion of the address for the first command block on the cbl. in linear mode it is a 32-bit linear address for the first command block on the cbl. it is accessed only if cuc equals start. 33
82596dx/sx rfa offset (address) in 82586 and 32-bit segmented modes this 16-bit quantity indicates the offset portion of the address for the receive frame area. in linear mode it is a 32-bit linear address for the receive frame area. it is accessed only if ruc equals start. scb statistical counters statistical counter operation # the cpu is responsible for clearing all error counters before initializing the 82596. the 82596 updates these counters by reading them, adding 1, and then writing them back to the scb. # the counters are wraparound counters. after reaching ffffffffh the counters wrap around to zero. # the 82596 updates the required counters for each frame. it is possible for more than one counter to be updated; multiple errors will result in all affected counters being updated. # the 82596 executes the read-counter/increment/write-counter operation without relinquishing the bus (locked operation). this is to ensure that no logical contention exists between the 82596 and the cpu due to both attempting to write to the counters simultaneously. in the dual-port memory configuration the cpu should not execute any write operation to a counter if lock is asserted. # the counters are 32-bits wide and their behavior is fully compatible with the ieee 802.3 standard. the 82596 supports all relevant statistics (mandatory, optional, and desired) through the status of the transmit and receive header and directly through scb statistics. crcerrs this 32-bit quantity contains the number of aligned frames discarded because of a crc error. this counter is updated, if needed, regardless of the ru state. alnerrs this 32-bit quantity contains the number of frames that both are misaligned (i.e., where crs deasserts on a nonoctet boundary) and contain a crc error. the counter is updated, if needed, regardless of the ru state. shrtfrm this 32-bit quantity contains the number of received frames shorter than the minimum frame length. the last three counters change function in monitor mode. rscerrs this 32-bit quantity contains the number of good frames discarded because there were no resources to contain them. frames intended for a host whose ru is in the no receive resources state, fall into this category. this counter is updated only if the ru is in the no resources state. when in moniitor mode, this counter counts the total number of frames. ovrnerrs this 32-bit quantity contains the number of frames known to be lost because the local system bus was not available. if the traffic problem lasts longer than the duration of one frame, the frames that follow the first are lost without an indicator, and they are not counted. this counter is updated, if needed, regardless of the ru state. rcvcdt this 32-bit counter contains the number of collisions detected during frame reception. this counter will only be updated if at least 64 bytes of data are received before the collision occurs. if a collision occurs before 64 bytes of data are received, the frame is counted as a short frame. if the collisions occurs in the preamble, no counters are incremented. 34
82596dx/sx action commands and operating modes this section lists all the action commands of the command unit command block list (cbl). each command contains the command field, the status and control fields, the link to the next action command, and any command-specific parameters. there are three basic types of action commands: 82596 configuration and setup, transmission, and diagnostics. the following is a list of the actual commands. # nop # individual address setup # configure # mc setup # transmit # tdr # dump # diagnose the 82596 has three addressing modes. in the 82586 mode all the action commands look exactly like those of the 82586. # 82586 mode. the 82596 software and memory structure is compatible with the 82586. # 32-bit segmented mode. the 82596 can access the entire system memory and use the two new memory structuresesimplified and flexibleewhile still using the segmented approach. this does not require any significant changes to existing software. # linear mode. the 82596 operates in a flat, linear, 4 gigabyte memory space without segmentation. it can also use the two new memory structures. in the 32-bit segmented mode there are some differences between the 82596 and 82586 action commands, mainly in programming and activating new 82596 features. those bits marked ``don't care'' in the compatible mode are not checked; however, we strongly recommend that those bits all be zeroes; this will allow future enchancements and extensions. in the linear mode all of the address offsets become 32-bit address pointers. all new 82596 features are accessible in this mode, and all bits previously marked ``don't care'' must be zeroes. the action commands, and all other 82596 memory structures, must begin on even byte boundaries, i.e., they must be word aligned. nop this command results in no action by the 82596 except for those performed in the normal command process- ing. it is used to manipulate the cbl manipulation. the format of the nop command is shown in figure 21. nope82586 and 32-bit segmented modes 31 16 odd word 15 0 even word els i xxxxxxxxxx000cbok 00000000000000 xxxxxxxxxxxxxxxxa15 a0 link offset 4 nopelinear mode 31 16 odd word 15 0 even word elsi 0000000000000cbok00000000000000 a31 a0 link address 4 figure 21 35
82596dx/sx where: link pointer e in the 82586 or 32-bit segmented modes this is a 16-bit offset to the next command block. in the linear mode this is the 32-bit address of the next command block. el e if set, this bit indicates that this command block is the last on the cbl. s e if set to one, suspend the cu upon completion of this cb. i e if set to one, the 82596 will generate an interrupt after execution of the command is complete. if i is not set to one, the cx bit will not be set. cmd (bits 16 18) e the nop command. value: 0h. bits 19 28 e reserved (zero in the 32-bit segmented and linear modes). c e this bit indicates the execution status of the command. the cpu initially resets it to zero when the command block is placed on the cbl. following a command completion, the 82596 will set it to one. b e this bit indicates that the 82596 is currently executing the nop command. it is initially reset to zero by the cpu. the 82596 sets it to one when execution begins and to zero when execution is completed. this bit is also set when the 82596 prefetches the com- mand. note: the c and b bits are modified in one operation. ok e indicates that the command was executed without error. if set to one no error occurred (command executed ok). if zero an error occur. individual address setup this command is used to load the 82596 with the individual address. this address is used by the 82596 for inserting the source address during transmission and recognizing the destination address during reception. after reset, and prior to individual address setup command execution, the 82596 assumes the broadcast address is the individual address in all aspects, i.e.: # this will be the individual address match reference. # this will be the source address of a transmitted frame (for al-loc e 0 mode only). the format of the individual address setup command is shown in figure 22. ia setupe82586 and 32-bit segmented modes 31 16 odd word 15 0 even word els i xxxxxxxxxx001cboka 0000000000000 individual address 1st byte a15 a0 link offset 4 6th byte 5th byte 4th byte 3rd byte 8 ia setupelinear mode 31 16 odd word 15 0 even word els i 0000000000001cboka0000000000000 a31 a0 link address 4 4th byte 3rd byte individual address 1st byte 8 6th byte 5th byte c figure 22 where: link address, e as per standard command block (see the nop command for details) el, b, c, i, s a e indicates that the command was abnormally terminated due to cu abort control command. if one, then the command was aborted, and if necessary it should be repeated. if this bit is zero, the command was not aborted. 36
82596dx/sx bits 19 28 e reserved (zero in the 32-bit segmented and linear modes). cmd (bits 16 18) e the address setup command. value: 1h. individual address e the individual address of the node, 0 to 6 bytes long. the least significant bit of the individual address must be zero for ethernet (see the command structure). however, no enforcement of 0 is provided by the 82596. thus, an individual address with 1 as its least significant bit is a valid individual address in all aspects. the default address length is 6 bytes long, as in 802.3. if a different length is used the ia setup command should be executed after the configure command. configure the configure command loads the 82596 with its operating parameters. it allows changing some of the parameters by specifying a byte count less than the maximum number of configuration bytes (11 in the 82586 mode, 14 in the 32-bit segmented and linear modes). the 82596 configuration depends on its mode of operation. # in the 82586 mode the maximum number of configuration bytes is 12. any number larger than 12 will be reduced to 12 and any number less than 4 will be increased to 4. when configuring the 12 th byte (byte 11 undefined) in 82586 mode this byte should be all ones. # the additional features of the serial side are disabled in the 82586 mode. # in both the 32-bit segmented and linear modes there are four additional configuration bytes, which hold parameters for additional 82596 features. if these parameters are not accessed, the 82596 will follow their default values. # for more detailed information refer to the 32-bit lan components user's manual. the format of the configure command is shown in figures 23, 24, and 25. 31 16 odd word 15 0 even word els i xxxxxxxxxx010cboka000 0000000000 byte 1 byte 0 a15 a0 link offset 4 byte 5 byte 4 byte 3 byte 2 8 byte 9 byte 8 byte 7 byte 6 12 xxxxxxxxxxxxxxxxxxxxxxxx byte 10 16 figure 23. configuree82586 mode 31 16 odd word 15 0 even word elsi 0000000000010cboka0000000000000 byte 1 byte 0 a15 a0 link offset 4 byte 5 byte 4 byte 3 byte 2 8 byte 9 byte 8 byte 7 byte 6 12 byte 13 byte 12 byte 11 byte10 16 figure 24. configuree32-bit segmented mode 37
82596dx/sx 31 16 odd word 15 0 even word elsi 0000000000010cboka0000000000000 a31 a0 link address 4 byte 3 byte 2 byte 1 byte 0 8 byte 7 byte 6 byte 5 byte 4 12 byte 11 byte 10 byte 9 byte 8 16 xxxxxxxxxxxxxxxx byte 13 byte 12 20 figure 25. configureelinear mode link address, e as per standard command block (see the nop command for details) el, b, c, i, s a e indicates that the command was abnormally terminated due to a cu abort control com- mand. if 1, then the command was aborted and if necessary it should be repeated. if this bit is 0, the command was not aborted. bits 19 28 e reserved (zero in the 32-bit segmented and linear modes) cmd (bits 16 18) e the configure command. value: 2h. the interpretation of the fields follows: 76543210 p x x x byte count byte 0 byte cnt (bits 0 3) byte count. number of bytes, including this one, that hold pa- rameters to be configured. prefetched (bit 7) enable the 82596 to write the prefetched bit in all prefetch rbds. note: the p bit is valid only in the new memory structure modes. in 82586 mode this bit is disabled (i.e., no prefetched mark). 7 0 monitor x x fifo limit byte 1 fifo limit (bits 0 3) fifo limit. monitor y (bits 6 7) receive monitor options. if the byte count of the configure command is less than 12 bytes then these monitor bits are ignored. default: c8h 7 0 savbf10000 resume e rd 0 byte 2 resume e rd (bit 1) 0e the 82596 does not reread the next cb on the list when a cu resume control command is issued. 1e the 82596 will reread the next cb on the list when a cu resume control command is issued. this is available only on the 82596b step- ping. sav bf (bit 7) 0e received bad frames are not saved in the memory. 1e received bad frames are saved in the memory. default: 40h 38
82596dx/sx 7 0 loop back preamble length no src address length mode add ins byte 3 adr len (bits 0 2) address length (any kind). no scr add ins (bit 3) no source address insertion. in the 82586 this bit is called al loc. pream len (bits 4 5) preamble length. lp bck mode (bits 6 7) loopback mode. default: 26h 7 0 bof metd exponential priority 0 linear priority byte 4 lin prio (bits 0 2) linear priority. exp prio (bits 4 6) exponential priority. bof metd (bit 7) exponential backoff method. default: 00h 7 0 inter frame spacing byte 5 interframe spacing interframe spacing. default: 60h 7 0 slot time - low byte 6 slot time (l) slot time, low byte. default: 00h 7 0 maximum retry number 0 slot time - high byte 7 slot time (h) slot time, high part. (bits 0 2) retry num (bits 4 7) number of transmission retries on collision. default: f2h 39
82596dx/sx 7 0 pad bit crc16/ no crc tx on man/ bc prm stuff crc32 inser no crs nrz dis mode byte 8 prm (bit 0) promiscuous mode. bc dis (bit 1) broadcast disable. manch/nrz (bit 2) manchester or nrz encoding. see specific timing require- ments for txc in manchester mode. tono crs (bit 3) transmit on no crs. nocrc ins (bit 4) no crc insertion. crc-16/crc-32 (bit 5) crc type. bit stf (bit 6) bit stuffing. pad (bit 7) padding. default: 00h 7 0 cdt src collision detect filter crs src carrier sense filter byte 9 crsf (bits 0 2) carrier sense filter (length). crs src (bit 3) carrier sense source. cdtf (bits 4 6) collision detect filter (length). cdt src (bit 7) collision detect source. default: 00h 7 0 minimum frame length byte 10 min frame len minimum frame length. default: 40h 7 0 monitor mc e all cdbsac autotx crcinm lngfld precrs byte 11 precrs (bit 0) preamble until carrier sense lngfld (bit 1) length field. enables padding at the end-of-carrier framing (802.3). crcinm (bit 2) rx crc appended to the frame in memory. autotx (bit 3) auto retransmit. cdbsac (bit 4) collision detect by source address recognition. mc e all (bit 5) enable to receive all mc frames. monitor (bits 6 7) receive monitor options. default: ffh 40
82596dx/sx 7 0 0fdx000000 byte 12 fdx (bit 6) enables full duplex operation. default: 00h 7 0 dis e bof mult e ia111111 byte 13 mult e ia (bit 6) multiple individual address. dis e bof (bit 7) disable the backoff algorithm. default: 3fh 41
82596dx/sx a reset (hardware or software) configures the 82596 according to the following defaults. table 4. configuration defaults parameter default value units/meaning address length ** 6 bytes a/l field location 0 located in fd * auto retransmit 1 auto retransmit enable bitstuffing/eoc 0 eoc broadcast disable 0 broadcast reception enabled * cdbsac 1 disabled cdt filter 0 bit times cdt src 0 external collision detection * crc in memory 1 crc not transferred to memory crc-16/crc-32 ** 0 crc-32 crs filter 0 0 bit times crs src 0 external crs * disbof 0 backoff enabled ext loopback 0 disabled exponential priority ** 0 802.3 algorithm exponential backoff method ** 0 802.3 algorithm * full duplex (fdx) 0 csma/cd protocol (no fdx) fifo threshold 8 tx: 32 bytes, rx: 64 bytes int loopback 0 disabled interframe spacing ** 96 bit times linear priority ** 0 802.3 algorithm * length field 1 padding disabled min frame length ** 64 bytes * mc all 1 disabled * monitor 11 disabled manchester/nrz 0 nrz * multi ia 0 disabled number of retries ** 15 maximum number of retries no crc insertion 0 crc appended to frame prefetch bit in rbd 0 disabled (valid only in new modes) preamble length ** 7 bytes * preamble until crs 1 disabled promiscuous mode 0 address filter on padding 0 no padding slot time ** 512 bit times save bad frame 0 discards bad frames transmit on no crs 0 disabled notes: 1. this configuration setup is compatible with the ieee 802.3 specification. 2. the asterisk `` * '' signifies a new configuration parameter not available in the 82586. 3. the default value of the auto retransmit configuration parameter is enabled (1). 4. double asterisk `` ** '' signifies ieee 802.3 requirements. 42
82596dx/sx multicast-setup this command is used to load the 82596 with the multicast-ids that should be accepted. as noted previously, the filtering done on the multicast-ids is not perfect and some unwanted frames may be accepted. this command resets the current filter and reloads it with the specified multicast-ids. the format of the multicast- addresses setup command is: 31 16 odd word 15 0 even word els i xxxxxxxxxx011cboka000000000000 x x mc count a15 a0 link offset 4th byte 1st byte multicast addresses list nth byte figure 26. mc setupe82586 and 32-bit segmented modes 31 16 odd word 15 0 even word els i 0000000000011cboka000000000000 a31 a0 link address 2nd byte 1st byte x x mc count multicast addresses list nth byte figure 27. mc setupelinear mode where: link address, e as per standard command block (see the nop command for details) el, b, c, i, s a e indicates that the command was abnormally terminated due to a cu abort control command. if one, then the command was aborted and if necessary it should be repeated. if this bit is zero, the command was not aborted. bits 19 28 e reserved (0 in both the 32-bit segmented and linear modes). cmd (bits 16 18) e the mc setup command value: 3h. mc-cnt this 14-bit field indicates the number of bytes in the mc list field. the mc cnt must be a multiple of the addr len; otherwise, the 82596 reduces the mc cnt to the nearest addr len multiple. mc cnt e 0 implies resetting the hash table which is equivalent to disabling the multicast filtering mechanism. mc list e a list of multicast addresses to be accepted by the 82596. the least significant bit of each mc address must be 1. note: the list is sequential; i.e., the most significant byte of an address is immediately followed by the least signifi- cant byte of the next address. e when the 82596 is configured to recognize multiple individual address (multi-ia), the mc-setup command is also used to set up the hash table for the individual address. the least significant bit in the first byte of each ia address must be 0. 43
82596dx/sx transmit this command is used to transmit a frame of user data onto the serial link. the format of a transmit command is as follows. 31 16 odd word 15 0 even word el s i x x x x x x x x x x 1 0 0 c b status bits maxcoll 0 a15 a0 tbd offset a15 a0 link offset 4 4th byte destination address 1st byte 8 length field 6th byte 12 figure 28. transmite82586 mode 31 16 odd word 15 0 even word el s i 0 0 0 0 0 0 0 0 nc sf 1 0 0 c b status bits maxcoll 0 a15 a0 tbd offset a15 a0 link offset 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eof 0 tcb count 8 4th byte destination address 1st byte 12 length field 6th byte 16 optional data figure 29. transmite32-bit segmented mode 31 16 odd word 15 0 even word el s i 0 0 0 0 0 0 0 0 nc sf 1 0 0 c b status bits maxcoll 0 a31 a0 link address 4 a31 a0 transmit buffer descriptor address 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eof 0 tcb count 12 4th byte destination address 1st byte 16 20 length field 6th byte optional data figure 30. transmitelinear mode 31 16 command word els i 00000000ncsf1002 uu 0: no crc insertion disable; when the 0: simplified mode, all the tx data is in configure command is configured to the transmit command block. the not insert the crc during transmit buffer descriptor address transmission the nc has no effect. field is all 1s. 1: no crc insertion enable; when the 1: flexible mode. data is in the tcb and configure command is configured to in a linked list of tbds. insert the crc during transmission the crc will not be inserted when nc e 1. 44
82596dx/sx where: el, b, c, i, s e as per standard command block (see the nop command for details). ok (bit 13) e error free completion. a (bit 12) e indicates that the command was abnormally terminated due to cu abort control command. if 1, then the command was aborted, and if necessary it should be repeated. if this bit is 0, the command was not aborted. bits 19 28 e reserved (0 in the 32-bit segmented and linear modes). cmd (bits 16 18) e the transmit command: 4h. status bit 11 e late collision. a late collision (a collision after the slot time is elapsed) is detected. status bit 10 e no carrier sense signal during transmission. carrier sense signal is monitored from the end of preamble transmission until the end of the frame check sequence for tonocrs e 1 (transmit on no carrier sense mode) it indicates that transmis- sion has been executed despite a lack of crs. for tonocrs e 0 (ethernet mode), this bit also indicates unsuccessful transmission (transmission stopped when lack of carrier sense has been detected). status bit 9 e transmission unsuccessful (stopped) due to loss of cts . status bit 8 e transmission unsuccessful (stopped) due to dma underrun; i.e., the system did not supply data for transmission. status bit 7 e transmission deferred, i.e., transmission was not immediate due to previous link activity. status bit 6 e heartbeat indicator, indicates that after a previously performed transmission, and before the most recently performed transmission, (interframe spacing) the cdt signal was monitored as active. this indicates that the ethernet transceiver colli- sion detect logic is performing properly. the heartbeat is monitored during the interframe spacing period. status bit 5 e transmission attempt was stopped because the number of collisions exceeded the maximum allowable number of retries. status bit 4 e 0 (reserved). max-col e the number of collisions experienced during this frame. max col e 0 plus s5 e 1 (bits 3 0) indicates 16 collisions. link offset e as per standard command block (see the nop for details). tbd pointer e in the 82586 and 32-bit segmented modes this is the offset of the first tx buffer descriptor containing the data to be transmitted. in the linear mode this is the 32- bit address of the first tx buffer descriptor on the list. if the tbd pointer is all 1s it indicates that no tbd is used. dest address e contains the destination address of the frame. the least significant bit (mc) indi- cates the address type. mc e 0: individual address. mc e 1: multicast or broadcast address. if the destination address bits are all 1s this is a broadcast address. length field e the contents of this 2-byte field are user defined. in 802.3 it contains the length of the data field. it is placed in memory in the same order it is transmitted; i.e., most significant byte first, least significant byte second. tcb count e this 14-bit counter indicates the number of bytes that will be transmitted from the transmit command block, starting from the third byte after the tcb count field (address n a 12 in the 32-bit segmented mode, n a 16 in the linear mode). the tcb count field can be any number of bytes (including an odd byte), this allows the user to transmit a frame with a header having an odd number of bytes. the tcb count field is not used in the 82586 mode. eof bit e indicates that the whole frame is kept in the transmit command block. in the simplified memory model it must be always asserted. 45
82596dx/sx the interpretation of what is transmitted depends on the no source address insertion configuration bit and the memory model being used. notes 1. the destination address and the length field are sequential of the length field immediately follows the most significant byte of the destination address. 2. in case the 82596 is configured with no source address insertion bit equal to 0, the 82596 inserts its configured source address in the transmitted frame. # in the 82586 mode, or when the simplified memory model is used, the destination and length fields of the transmitted frame are taken from the transmit command block. # if the flexible memory model is used, the destination and length fields of the transmitted frame can be found either in the tcb or tbd, depending on the tcb count. 3. if the 82596 is configured with the address/length field location equal to 1, the 82596 does not insert its configured source address in the transmitted frame. the first (2 c address length) a 2 bytes of the transmitted frame are interpreted as destination address, source address, and length fields respectively. the location of the first transmitted byte depends on the operational mode of the 82596: # in the 82586 mode, it is always the first byte of the first tx buffer. # in both the 32-bit segmented and linear modes it depends on the sf bit and tcb count: e in the simplified memory mode the first transmitted byte is always the third byte after the tcb count field. e in the flexible mode, if the tcb count is greater than 0 then it is the third byte after the tcb count field. if tcb count equals 0 then it is first byte of the first tx buffer. # transmit frames shorter than six bytes are invalid. the transmission will be aborted (only in 82586 mode) because of a dma underrun. 4. frames which are aborted during transmission are jammed. such an interruption of transmission can be caused by any reason indicated by any of the status bits 8, 9, 10 and 12. jamming rules 1. jamming will not start before completion of preamble transmission. 2. collisions detected during transmission of the last 11 bits will not result in jamming. the format of a transmit buffer descriptor is: 82586 mode 31 16 odd word 15 0 13 even word next tbd offset eof x size (act count) 0 xxxxxxxx transmit buffer address 4 32-bit segmented mode 31 16 odd word 15 0 13 even word next tbd offset eof 0 size (act count) 0 transmit buffer address 4 linear mode 31 16 odd word 15 0 13 even word 0000000000000000eof0 size (act count) 0 next tbd address 4 transmit buffer address 8 figure 31 46
82596dx/sx where: eof e this bit indicates that this tbd is the last one associated with the frame being transmitted. it is set by the cpu before transmit. size (act count) e this 14-bit quantity specifies the number of bytes that hold information for the current buffer. it is set by the cpu before transmission. next tbd address e in the 82586 and 32-bit segmented modes, it is the offset of the next tbd on the list. in the linear mode this is the 32-bit address of the next tbd on the list. it is meaningless if eof e 1. buffer address e the starting address of the memory area that contains the data to be sent. in the 82586 mode, this is a 24-bit address (a31 a24 are considered to be zero). in the 32-bit segmented and linear modes this is a 32-bit address. this buffer can be byte aligned for the 82596 b-step. tdr this operation activates time domain reflectometry, which is a mechanism to detect open or short circuits on the link and their distance from the diagnosing station. the tdr command has no parameters. the tdr transmit sequence was changed, compared to the 82586, to form a regular transmission. the tdr command is designed to be used statically. make sure that both the cu and ru are idle before attempting a tdr command. the tdr bit stream is as follows. e preamble e source address e another source address (the tdr frame is transmitted back to the sending station, so dest adr e src adr). e data field containing 7eh patterns. e jam pattern, which is the inverse crc of the transmitted frame. maximum length of the tdr frame is 2048 bits. if the 82596 senses collision while transmitting the tdr frame it transmits the jam pattern and stops the transmission. the 82596 then triggers an internal timer (stc); the timer is reset at the beginning of transmission and reset if crs is returned. the timer measures the time elapsed from the start of transmission until an echo is returned. the echo is indicated by collision detect going active or a drop in the carrier sense signal. the following table lists the possible cases that the 82596 is able to analyze. conditions of tdr as interpreted by the 82596 transceiver type ethernet non ethernet condition carrier sense was inactive for 2048-bit-time short or open on the na periods transceiver cable carrier sense signal dropped short on the ethernet cable na collision detect went active open on the ethernet cable open on the serial link the carrier sense signal did not drop or the no problem no problem collision detect did not go active within 2048-bit time period an ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the carrier sense signal while transmitting. a non-ethernet transceiver is defined as one that does not do so. 47
82596dx/sx the format of the time domain reflectometer command is: 82586 and 32-bit segmented modes 31 16 odd word 15 0 even word el s i x xxxxxxxxx101cbok00 00000000000 lnk xvr et et x time a15 a0 link offset ok prb opn srt (11 bits) linear mode 31 16 odd word 15 0 even word els i 0000000000101cbok0000000000000 a31 a0 link address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lnk xvr et et x time ok prb opn srt (11 bits) figure 32. tdr where: link address, e as per standard command block (see the nop command for details). el, b, c, i, s a e indicates that the command was abnormally terminated due to cu abort control command. if one, then the command was aborted, and if necessary it should be repeated. if this bit is zero, the command was not aborted. bits 19 28 e reserved (0 in the 32-bit segmented and linear modes). cmd (bits 16 18) e the tdr command. value: 5h. time e an 11-bit field that specifies the number of txc cycles that elapsed before an echo was observed. no echo is indicated by a reception consisting of ``1s'' only. be- cause the network contains various elements such as transceiver links, transceiv- ers, ethernet, repeaters etc., the time is not exactly proportional to the problems distance. lnk ok (bit 15) e no link problem identified. time e 7ffh. xcvr prb (bit 14) e indicates a transceiver problem. carrier sense was inactive for 2048-bit time peri- od. lnk ok e 0. time e 7ffh. et opn (bit 13) e the transmission line is not properly terminated. collision detect went active and lnk ok e 0. et srt (bit 12) e there is a short circuit on the transmission line. carrier sense signal dropped and lnk ok e 0. 48
82596dx/sx dump this command causes the contents of various 82596 registers to be placed in a memory area specified by the user. it is supplied as a 82596 self-diagnostic tool, and to provide registers of interest to the user. the format of the dump command is: 82586 and 32-bit segmented modes 31 16 odd word 15 0 even word els i xxxxxxxxxx110cbok0000000000000 a15 a0 buffer offset a15 a0 link offset linear mode 31 16 odd word 15 0 even word els i xxxxxxxxxx110cbok0000000000000 a31 a0 link address a31 a0 buffer address figure 33. dump where: link address, e as per standard command block (see the nop command for details). el, b, c, i, s ok e indicates error free completion. bits 19 28 e reserved (0 in the 32-bit segmented and linear modes). cmd (bits 16 18) e the dump command. value: 6h. buffer pointer e in the 82586 and 32-bit segmented modes this is the 16-bit-offset portion of the dump area address. in the linear mode this is the 32-bit linear address of the dump area. dump area information format # the 82596 is not dump compatible with the 82586 because of the 32-bit internal architecture. in 82586 mode the 82596 will dump the same number of bytes as the 82586. the compatible data will be marked with an asterisk. # in 82586 mode the dump area is 170 bytes. # the dump area format of the 32-bit segmented and linear modes is described in figure 35. # the size of the dump area of the 32-bit segmented and linear modes is 304 bytes. # when the dump is executed by the port command an extra word will be appended to the dump area. the extra word is a copy of the dump area status word (containing the c, b, and ok bits). the c and ok bits are set when the 82596 has completed the port dump command. 49
82596dx/sx 1514131211109876543210 dma control register * 00 configure bytes 3, 2 02 configure bytes 5, 4 04 configure bytes 7, 6 06 configure bytes 9, 8 08 configure bytes 10 0a i.a. bytes 1, 0 * 0c i.a. bytes 3, 2 * 0e i.a. bytes 5, 4 * 10 last t.x. status * 12 t.x. crc bytes 1, 0 * 14 t.x. crc bytes 3, 2 * 16 r.x. crc bytes 1, 0 * 18 r.x. crc bytes 3, 2 * 1a r.x. temp memory 1, 0 * 1c r.x. temp memory 3, 2 * 1e r.x. temp memory 5, 4 * 20 last received status * 22 hash register bytes 1, 0 * 24 hash register bytes 3, 2 * 26 hash register bytes 5, 4 * 28 hash register bytes 7, 6 * 2a slot time counter * 2c wait time counter * 2e micro machine ** 30 . register file . . 60 bytes 6a micro machine lfsr ** 6c micro machine 6e . flag array . . 14 bytes 7a queue memory ** 7c . cu port . 8 bytes 82 micro machine alu ** 84 reserved ** 86 m.m. temp a rotate r ** 88 m.m. temp a ** 8a t.x. dma byte count ** 8c m.m. input port address ** 8e t.x. dma address ** 90 m.m. output port ** 92 r.x. dma byte count ** 94 m.m. output port address register ** 96 r.x. dma address ** 98 reserved ** 9a bus throttle timers 9c diu control register ** 9e reserved ** a0 dma control register ** a2 biu control register ** a4 m.m. dispatcher register ** a6 m.m. status register ** a8 figure 34. dump area formate82586 mode note: * the 82596 is not dump compatible with the 82586 because of the 32-bit internal architecture. in 82586 mode the 82596 will dump the same number of bytes as the 82586. the compati- ble data will be marked with an aster- isk. ** these bytes are not user defined, results may vary from dump com- mand to dump command. 50
82596dx/sx 31 0 configure bytes 5, 4, 3, 2 00 configure bytes 9, 8, 7, 6 04 configure bytes 13, 12, 11, 10 08 i.a. bytes 1, 0 x x x x x x x x 0c i.a. bytes 5, 2 10 tx crc bytes 0, 1 last t.x. status 14 rx crc bytes 0, 1 tx crc bytes 3, 2 18 rx temp memory 1, 0 rx crc bytes 3, 2 1c r.x. temp memory 5, 2 20 hash registers 1, 0 last r.x. status 24 hash register bytes 5, 2 28 slot time counter hash registers 7, 6 2c receive frame length wait-time counter 30 micro machine ** 34 . register file . . 128 bytes b0 micro machine lfsr ** b4 micro machine ** b8 . flag array . . 28 bytes d0 m.m. input port ** d4 16 bytes e0 micro machine alu ** e4 reserved ** e8 m.m. temp a rotate r. ** ec m.m. temp a ** f0 t.x. dma byte count ** f4 m.m. input port address register ** f8 t.x. dma address ** fc m.m. output port register ** 100 r.x. dma byte count ** 104 m.m. output port address register ** 108 r.x. dma address register ** 10c reserved ** 110 bus throttle timers 114 diu control register ** 118 reserved ** 11c dma control register ** 120 biu control register ** 124 m.m. dispatcher reg. ** 128 m.m. status register ** 12c figure 35. dump area formatelinear and 32-bit segmented mode note: the 82596 is not dump compatible with the 82586 because of the 32-bit internal architecture. in 82586 mode the 82596 will dump the same number of bytes as the 82586. the compati- ble data will be marked with an aster- isk. ** these bytes are not user defined, results may vary from dump com- mand to dump command. 51
82596dx/sx diagnose the diagnose command triggers an internal self-test procedure that checks internal 82596 hardware, which includes: # exponential backoff random number generator (linear feedback shift register). # exponential backoff timeout counter. # slot time period counter. # collision number counter. # exponential backoff shift register. # exponential backoff mask logic. # timer trigger logic. this procedure checks the operation of the backoff block, which resides in the serial side and is not easily controlled. the diagnose command is performed in two phases. the format of the 82596 diagnose command is: 82586 and 32-bit segmented modes 31 16 odd word 15 0 even word els i xxxxxxxxxx111cbok0f00000000000 xxxxxxxxxxxxxxxxa15 a0 link offset linear mode 31 16 odd word 15 0 even word els i 0000000000111cbok0f00000000000 a31 a0 link address figure 36. diagnose where: link address, e as per standard command block (see the nop command for details). el, b, c, i, s bits 19 28 e reserved (0 in the 32-bit segmented and linear modes). cmd (bits 16 18) e the diagnose command. value: 7h. ok (bit 13) e indicates error free completion. f (bit 11) e indicates that the self-test procedure has failed. receive frame descriptor each received frame is described by one receive frame descriptor (see figure 37). two new memory structures are available for the received frames. the structures are available only in the linear and 32-bit segmented modes. 52
82596dx/sx 290219 15 figure 37. the receive frame area simplified memory structure the first is the simplified memory structure, the data section of the received frame is part of the rfd and is located immediately after the length field. receive buffer descriptors are not used with the simplified struc- ture, it is primarily used to make programming easier. if the length of the data area described in the size field is smaller than the incoming frame, the following happens. 1. the received frame is truncated. 2. the no resource error counter is updated. 3. if the 82596 is configured to save bad frames the rfd is not reused; otherwise, the same rfd is used to hold the next received frame, and the only action taken regarding the truncated frame is to update the counter. 4. the 82596 continues to receive the next frame in the next rfd. 53
82596dx/sx note that this sequence is very useful for monitoring. if the 82596 is configured to save bad frames, to receive in promiscuous mode, and to use the simplified memory structure, any programmed length of received data can be saved in memory. the simplified memory structure is shown in figure 38. 290219 16 figure 38. rfa simplified memory structure flexible memory structure the second structure is the flexible memory structure, the data structure of the received frame is stored in both the rfd and in a linked list of receive buffersereceive buffer descriptors. the received frame is placed in the rfd as configured in the size field. any remaining data is placed in a linked list of rbds. the flexible memory structure is shown in figure 39. 54
82596dx/sx buffers on the receive side can be different lengths. the 82596 will not place more bytes into a buffer than indicated in the associated rbd. the 82596 will fetch the next rbd before it is needed. the 82596 will attempt to receive frames as long as the fbl is not exhausted. if there are no more buffers, the 82596 receive unit will enter the no resources state. before starting the ru, the cpu must place the fbl pointer in the rbd pointer field of the first rfd. all remaining rbd pointer fields for subsequent rfds should be ``1s.'' if the receive frame descriptor and the associated receive buffers are not reused (e.g., the frame is properly received or the 82596 is configured to save bad frames), the 82596 writes the address of the next free rbd to the rbd pointer field of the next rfd. receive buffer descriptor (rbd) the rbds are used to store received data in a flexible set of linked buffers. the portion of the frame's data field that is outside the rfd is placed in a set of buffers chained by a sequence of rbds. the rfd points to the first rbd, and the last rbd is flagged with an eof bit set to 1. each buffer in the linked list of buffers related to a particular frame can be any size up to 2 14 bytes but must be word aligned (begin on an even numbered byte). this ensures optimum use of the memory resources while maintaining low overhead. all buffers in a frame are filled with the received data except for the last, in which the actual count can be smaller than the allocated buffer space. 290219 17 figure 39. rfa flexible memory structure 55
82596dx/sx 31 16 odd word 15 0 even word elsxxxxxxxxxxxxxxcbok0 status bits 0 000000 a15 a0 rbd offset a15 a0 link offset 4 4th byte destination address 1st byte 8 source address 1st byte 6th byte 12 6th byte 4th byte 16 xxxxxxxxxxxxxxxx length field 20 figure 40. receive frame descriptore82586 mode 31 16 odd word 15 0 even word els0000000000sf000 c bok status bits 0 a15 a0 rbd offset a15 a0 link offset 4 0 0 size eof f actual count 8 4th byte destination address 1st byte 12 source address 1st byte 6th byte 16 6th byte 4th byte 20 length field 24 optional data area figure 41. receive frame descriptore32-bit segmented mode 31 16 odd word 15 0 even word els0000000000sf000 c bok status bits 0 a31 a0 link address 4 a31 a0 receive buffer descriptor address 8 0 0 size eof f actual count 12 4th byte destination address 1st byte 16 source address 1st byte 6th byte 20 6th byte 4th byte 24 length field 28 optional data area figure 42. receive frame descriptorelinear mode 56
82596dx/sx where: el e when set, this bit indicates that this rfd is the last one on the rdl. s e when set, this bit suspends the ru after receiving the frame. sf e this bit selects between the simplified or the flexible mode. 0 e simplified mode, all the rx data is in the rfd. rbd address field is all ``1s.'' 1 e flexible mode. data is in the rfd and in a linked list of receive buffer de- scriptors. c e this bit indicates the completion of frame reception. it is set by the 82596. b e this bit indicates that the 82596 is currently receiving this frame, or that the 82596 is ready to receive the frame. it is initially set to 0 by the cpu. the 82596 sets it to 1 when reception set up begins, and to 0 upon completion. the c and b bits are set during the same operation. ok (bit 13) e frame received successfully, without errors. rfds with bit 13 equal to 0 are possi- ble only if the save bad frames configuration option is selected. otherwise all frames with errors will be discarded, although statistics will be collected on them. status e the results of the receive operation. defined bits are, bit 12: length error if configured to check length bit 11: crc error in an aligned frame bit 10: alignment error (crc error in misaligned frame) bit 9: ran out of buffer spaceeno resources bit 8: dma overrun failure to acquire the system bus. bit 7: frame too short. bit 6: no eop flag (for bit stuffing only) bit 5: when the sf bit equals zero, and the 82596 is configured to save bad frames, this bit signals that the received frame was truncated. otherwise it is zero. bits 2 4: zeros bit 1: when it is zero, the destination address of the received frame matches the ia address. when it is 1, the destination address of the received frame does not match the individual address. for example, a multicast address or broadcast address will set this bit to a 1. bit 0: receive collision. a collision is detected during reception, and the colli- sion occurred after the destination address was received. link address e a 16-bit offset (32-bit address in the linear mode) to the next receive frame descriptor. the link address of the last frame can be used to form a cyclical list. rbd pointer e the offset (address in the linear mode) of the first rbd containing the received frame data. an rbd pointer of all ones indicates no rbd. eof e these fields are for the simplified and flexible memory models. they are exactly f the same as the respective fields in the receive buffer descriptor. see the next section for detailed explanation of their functions. size act count mc e multicast bit. e destination the contents of the destination address of the receive frame. the field is 0 to 6 address bytes long. source address e the contents of the source address field of the received frame. it is 0 to 6 bytes long. 57
82596dx/sx length field e the contents of this 2-byte field are user defined. in 802.3 it contains the length of the data field. it is placed in memory in the same order it is received, i.e., most significant byte first, least significant byte second. notes 1. the destination address, source address and length fields are packed, i.e., one field immediately follows the next. 2. the affect of address/length location (no source address insertion) configuration parameter while re- ceiving is as follows: e 82586 mode: the destination address, source address and length field are not used, they are placed in the rx data buffers. e 32-bit segmented and linear modes: when the simplified memory model is used, the destination address, source address and length fields reside in their respective fields in the rfd. when the flexible memory strucrture is used the destination address, source address, and length field locations depend on the size field of the rfd. they can be placed in the rfd, in the rx data buffers, or partially in the rfd and the rest in the rx data buffers, depending on the size field value. 82586 mode 31 16 odd word 15 0 even word a15 a0 next rbd offset eof f actual count 0 xxxxxxxxa23 a0 receive buffer address 4 xxxxxxxxxxxxxxxxelx size 8 32-bit segmented mode 31 16 odd word 15 0 even word a15 a0 next rbd offset eof f actual count 0 a31 a0 receive buffer address 4 0000000000000000elp size 8 linear mode 31 16 odd word 15 0 even word 0000000000000000eoff actual count 0 a31 a0 next rbd address 4 a31 a0 receive buffer address 8 0000000000000000elp size figure 43. receive buffer descriptor 58
82596dx/sx where: eof e indicates that this is the last buffer related to the frame. it is cleared by the cpu before starting the ru, and is written by the 82596 at the end of reception of the frame. f e indicates that this buffer has already been used. the actual count has no meaning unless the f bit equals one. this bit is cleared by the cpu before starting the ru, and is set by the 82596 after the associated buffer has been. this bit has the same meaning as the complete bit in the rfd and cb. act count e this 14-bit quantity indicates the number of meaningful bytes in the buffer. it is cleared by the cpu before starting the ru, and is written by the 82596 after the associated buffer has already been used. in general, after the buffer is full, the actual count value equals the size field of the same buffer. for the last buffer of the frame, actual count can be less than the buffer size. next bd address e the offset (absolute address in the linear mode) of the next rbd on the list. it is meaningless if el e 1. buffer address e the starting address of the memory area that contains the received data. in the 82586 mode, this is a 24-bit address (with pins a24 a31 e 0). in the 32-bit seg- mented and linear modes this is a 32-bit address. el e indicates that the buffer associated with this rbd is last in the fbl. p e this bit indicates that the 82596 has already prefetched the rbds and any change in the rbd data will be ignored. this bit is valid only in the new 82596 memory modes, and if this feature has been enabled during configure command. the 82596 prefetches the rbds in locked cycles; after prefetching the rbd the 82596 performs a write cycle where the p bit is set to one and the rest of the data remains unchanged. the cpu is responsible for resetting it in all rbds. the 82596 will not check this bit before setting it. size e this 14-bit quantity indicates the size, in bytes, of the associated buffer. this quan- tity must be an even number. 59
82596dx/sx pga package thermal specification parameter thermal resistance i jc 3 c/w i ja 24 c/w electrical and timing characteristics absolute maximum ratings storage temperature b 65 cto a 150 c case temperature under bias b 65 cto a 110 c supply voltage with respect to v ss b 0.5v to a 6.5v voltage on other pins b 0.5v to v cc a 0.5v d.c. characteristics t c e 0 cto a 85 c, v cc e 5v g 10% clk2 and le/be have mos levels (see v mil ,v mih ). all other signals have ttl levels (see v il ,v ih ,v ol ,v oh ). symbol parameter min max units notes v il input low voltage (ttl) b 0.3 a 0.8 v v ih input high voltage (ttl) 2.0 v cc a 0.3 v v mil input low voltage (mos) b 0.3 a 0.8 v v mih input high voltage (mos) 3.7 v cc a 0.3 v v ol output low voltage (ttl) 0.45 v i ol e 4.0 ma v cil rxc , txc input low voltage b 0.5 0.6 v v cih rxc , txc input high voltage 3.3 v cc a 0.5 v v oh output high voltage (ttl) 2.4 v i oh e 0.9ma 1 ma i li input leakage current g 15 m a0 s v in s v cc i lo output leakage current g 15 m a 0.45 k v out k v cc c in capacitance of input buffer 10 pf fc e 1 mhz c out capacitance of input/output 12 pf fc e 1 mhz buffer c clk clk capacitance 20 pf fc e 1 mhz i cc power supply 150 ma at 20 mhz for the 82596sx i cc typical e 90 ma i cc power supply 200 ma at 25 mhz i cc typical e 100 ma i cc power supply 300 ma at 33 mhz i cc typical e 150 ma 60
82596dx/sx a.c. characteristics 82596dx c-step input/output system timings t c e 0 cto a 85 ,v cc e 5v g 10% these timings assume the c l on all outputs is 50 pf unless otherwise specified. c l can be 20 pf to 120 pf, however, timings must be derated. all timing requirements are given in nanoseconds. symbol parameter 25 mhz notes min max operating frequency 12.5 mhz 25 mhz clk2/2 t1 clk2 period 20 40 t2 clk2 high 4 3.7v t3 clk2 low 5 0.8v t4 clk2 rise time e 7 0.8v to 3.7v t5 clk2 fall time e 7 3.7v to 0.8v t13 ca and breq setup time 7 1, 2, 3 t14 breq hold time 3 1, 2, 3 t14a ca hold time 5 1, 2, 3 t26 ca and breq, port pulse width 4 t1 3 t25 int valid delay 1 26 t6 bex valid delay 3 17 t6b lock valid delay 3 21 t6c a2 a31 valid delay 3 18 t7 bex , lock , and a2 a31 float delay 4 30 t8 w/r and ads valid delay 3 21 t9 w/r and ads float delay 4 30 t10 d0 d31 write data valid delay 3 19 t11 d0 d31 write data float delay 4 22 t27 d0 d31 cpu port access setup time 7 2 t28 d0 d31 cpu port access hold time 5 2 t29 port setup time 7 2 t30 port hold time 3 2 t17 rdy setup time 9 2 t18 rdy hold time 3 2 t19 d0 d31 read setup time 7 2 t20 d0 d31 read hold time 5 2 t12 hold valid delay 3 22 t21 hlda setup time 10 1, 2 t22a hlda hold time 3 1, 2 t23 reset setup time 10 2 t24 reset hold time 3 2 note: timings shown are for the 82596ca c-stepping. for information regarding timings for the 82596ca a1 or b-step, contact your local intel representative. 61
82596dx/sx a.c. characteristics (continued) 82596dx c-step input/output system timings t c e 0 cto a 85 c, v cc e 5v g 5% these timings assume the c l on all outputs is 50 pf unless otherwise specified. c l can be 20 pf to 120 pf, however, timings must be derated. all timing requirements are given in nanoseconds. symbol parameter 33 mhz notes min max operating frequency 12.5 mhz 33 mhz clk2/2 t1 clk2 period 15 40 t2 clk2 high 4.5 3.7v t3 clk2 low 4.5 0.8v t4 clk2 rise time e 4 3.7v to 0.8v t5 clk2 fall time e 4 0.8v to 3.7v t13 ca and breq setup time 7 1, 2, 3 t14 breq hold time 3 1, 2, 3 t14a ca hold time 5 1, 2, 3 t26 ca and breq, port pulse width 4 t1 3 t25 int valid delay 1 20 t6 bex valid delay 3 17 t6b lock valid delay 3 16 t6c a2 a31 valid delay 3 18 t7 bex , lock , and a2 a31 float delay 4 20 t8 w/r and ads valid delay 3 16 t9 w/r and ads float delay 4 20 t10 d0 d31 write data valid delay 3 19 t11 d0 d31 write data float delay 4 17 t27 d0 d31 cpu port access setup time 5 2 t28 d0 d31 cpu port access hold time 3 2 t29 port setup time 7 2 t30 port hold time 3 2 t17 rdy setup time 8 2 t18 rdy hold time 3 2 t19 d0 d31 read setup time 5.5 2 t20 d0 d31 read hold time 4 2 t12 hold valid delay 3 19 t21 hlda setup time 8 1, 2 t22a hlda hold time 3 1, 2 t23 reset setup time 9 2 t24 reset hold time 3 2 note: timings shown are for the 82596ca c-stepping. for information regarding timings for the 82596ca a1 or b-step, contact your local intel representative. 62
82596dx/sx a.c. characteristics (continued) 82596sx c-step input/output system timings t c e 0 cto a 85 c, v cc e 5v g 10% these timings assume the c l on all outputs is 50 pf unless otherwise specified. c l can be 20 pf to 120 pf, however, timings must be derated. all timing requirements are given in nanoseconds. symbol parameter 20 mhz notes min max operating frequency 12.5 mhz 20 mhz clk2/2 t1 clk2 period 25 40 t2 clk2 high 8 at 2.0v t3 clk2 low 8 at 2.0v t4 clk2 rise time e 8 0.8v to 3.7v t5 clk2 fall time e 8 3.7v to 0.8v t13 ca and breq setup time 10 1, 2, 3 t14 breq hold time 7 1, 2, 3 t14a ca hold time 8 1, 2, 3 t26 ca and breq, port pulse width 4 t1 3 t25 int valid delay 1 35 t6 bhe , ble , lock , bon, and a1 a31 3 30 valid delay t7 bhe , ble , lock , bon, and a1 a31 4 30 float delay t8 w/r and ads valid delay 3 26 t9 w/r and ads float delay 4 30 t10 d0 d15 write data valid delay 3 38 t11 d0 d15 write data float delay 4 27 t27 d0 d15 cpu port access setup time 9 2 t28 d0 d15 cpu port access hold time 6 2 t29 port setup time 10 2 t30 port hold time 7 2 t17 rdy setup time 12 2 t18 rdy hold time 4 2 t19 d0 d15 read setup time 9 2 t20 d0 d15 read hold time 5 2 t12 hold valid delay 3 28 t21 hlda setup time 15 1, 2 t22a hlda hold time 7 1, 2 t23 reset setup time 12 1, 2 t24 reset hold time 4 1, 2 note: timings shown are for the 82596ca c-stepping. for information regarding timings for the 82596ca a1 or b-step, contact your local intel representative. 63
82596dx/sx a.c. characteristics (continued) 82596sx c-step input/output system timings t c e 0 cto a 85 c, v cc e 5v g 10% these timings assume the c l on all outputs is 50 pf unless otherwise specified. c l can be 20 pf to 120 pf, however, timings must be derated. all timing requirements are given in nanoseconds. symbol parameter 16 mhz notes min max operating frequency 12.5 mhz 16 mhz clk2/2 t1 clk2 period 31 40 t2 clk2 high 9 2.0v t3 clk2 low 9 2.0v t4 clk2 rise time e 8 0.8v to 3.7v t5 clk2 fall time e 8 3.7v to 0.8v t13 ca and breq setup time 11 1, 2, 3 t14 ca and breq hold time 8 1, 2, 3 t26 ca and breq, port pulse width 4 t1 3 t25 int valid delay 1 40 t6 bhe , ble , bon, and a1 a31 valid delay 3 36 t6b lock y valid delay 1 33 t7 bhe , ble , lock , bon, and a1 a31 float delay 4 40 t8 w/r and ads valid delay 1 33 t9 w/r and ads float delay 4 35 t10 d0 d15 write data valid delay 3 40 t11 d0 d15 write data float delay 4 35 t27 d0 d15 cpu port access setup time 9 2 t28 d0 d15 cpu port access hold time 6 2 t29 port setup time 11 2 t30 port hold time 8 2 t17 rdy setup time 19 2 t18 rdy hold time 6 2 t19 d0 d15 read setup time 9 2 t20 d0 d15 read hold time 6 2 t12 hold valid delay 2 33 64
82596dx/sx a.c. characteristics (continued) 82596sx c-step input/output system timings t c e 0 cto a 85 c, v cc e 5v g 10% (continued) these timings assume the c l on all outputs is 50 pf unless otherwise specified. c l can be 20 pf to 120 pf, however, timings must be derated. all timing requirements are given in nanoseconds. symbol parameter 16 mhz notes min max t21 hlda setup time 15 1, 2 t22a hlda hold time 7 1, 2 t23 reset setup time 13 1, 2 t24 reset hold time 4 1, 2 notes: timings shown are for the 82596ca c-stepping. for information regarding timings for the 82596ca a1 or b-step, contact your local intel representative. 1. reset, hlda, and ca are internally synchronized. this timing is to guarantee recognition at next clock for reset, hlda, and ca. 2. all set-up, hold, and delay timings are at the maximum frequency specification fmax, and must be derated according to the following equation for operation at lower frequencies: tderated e (fmax/fopr) c t where: tderated e specifies the value to derate the specification. fmax e maximum operating frequency. fopr e actual operating frequency. t e specification at maximum frequency. this calculation only provides a rough estimate for derating the frequency. for more detailed information contact your intel sales office for the data sheet supplement. 3. ca is internally synchronized; if the setup and hold times are met then ca needs to be only 2 t1. breq and port are not internally synchronized. breq must meet setup and hold times and need only be 2 t1 wide. 65
82596dx/sx transmit/receive clock parameters symbol parameter 20 mhz notes min max t36 txc cycle 50 1, 3 t38 txc rise time 5 1 t39 txc fall time 5 1 t40 txc high time 19 1, 3 t41 txc low time 18 1, 3 t42 txd rise time 10 4 t43 txd fall time 10 4 t44 txd transition 20 2, 4 t45 txc low to txd valid 25 4, 6 t46 txc low to txd transition 25 2, 4 t47 txc high to txd transition 25 2, 4 t48 txc low to txd high (at end of transition) 25 4 rts and cts parameters t49 txc low to rts low, 25 5 time to activate rts t50 cts low to txc low, cts setup time 20 t51 txc low to cts invalid, cts hold time 10 7 t52 txc low to rts high 25 5 receive clock parameters t53 rxc cycle 50 1, 3 t54 rxc rise time 5 1 t55 rxc fall time 5 1 t56 rxc high time 19 1 t57 rxc low time 18 1 received data parameters t58 rxd setup time 20 6 t59 rxd hold time 10 6 66
82596dx/sx transmit/receive clock parameters (continued) symbol parameter 20 mhz notes min max received data parameters (continued) t60 rxd rise time 10 t61 rxd fall time 10 crs and cdt parameters t62 cdt low to txc high 20 external collision detect setup time t63 txc high to cdt inactive, cdt hold time 10 t64 cdt low to jam start 10 t65 crs low to txc high, 20 carrier sense setup time t66 txc high to crs inactive, crs hold time 10 t67 crs high to jamming start, 12 (internal collision detect) t68 jamming period 11 t69 crs high to rxc high, 30 crs inactive setup time t70 rxc high to crs high, 10 crs inactive hold time interframe spacing parameters t71 interframe delay 9 external loopback-pin parameters t72 txc low to lpbk low t36 4 t73 txc low to lpbk high t36 4 notes: 1. special mos levels, v cil e 0.9v and v cih e 3.0v. 2. manchester only. 3. manchester. needs 50% duty cycle. 4. 1 ttl load a 50 pf. 5. 1 ttl load a 100 pf. 6. nrz only. 7. abnormal end of transmissionects expires before rts. 8. normal end to transmission. 9. programmable value: t71 e n ifs # t36 where: n ifs e the ifs configuration value (if n ifs is less than 12 then n ifs is forced to 12). 10. programmable value: t64 e (n cdf # t36) a x # t36 (if the collision occurs after the preamble) where: n cdf e the collision detect filter configuration value, and x e 12, 13, 14, or 15 11. t68 e 32 # t36 12. programmable value: t67 e (n csf # t36) a x # t36 where: n csf e the carrier sense filter configuration value, and x e 12, 13, 14, or 15 13. to guarantee recognition on the next clock. 67
82596dx/sx 82596dx/sx bus operation the following figures show thae basic bus cycles for the 82596dx and 82596sx. for more details refer to the 32-bit lan components manual. 290219 42 figure 44. basic 82596dx bus cycles 290219 43 figure 45. basic 82596sx bus cycles 68
82596dx/sx system interface a.c. timing characteristics the measurements should be done at: # t c e 0 c85 c, v cc e 5v g 10%, c e 50 pf unless otherwise specified. # a.c. testing inputs are driven at 2.4v for a logic ``1'' and 0.45v for a logic ``0''. # timing measurements are made at 1.5v for both logic ``1'' and ``0''. # rise and fall time of inputs and outputs signals are measured between 0.8v and 2.0v respectively unless otherwise specified. # all timings are relative to clk2 crossing the 1.5v level. # all a.c. parameters are valid only after 100 m s from power up. 290219 18 290219 19 figure 46. clk2 timings two types of timing specifications are presented below: 1. input timingeminimum setup and hold times. 2. output timingseoutput delays and float times from clk2 rising edge. figure 45 defines how the measurements should be done: 290219 20 legend: ts e input setup time th e input hold time tn e minimum output delay or mininum float delay tx e maximum output delay or maximum float delay figure 47. drive levels and measurements points for a.c. specifications 69
82596dx/sx input waveforms ts e t13, t15, t17, t19, t21, t23, t27, t29, t31 th e t14, t16, t18, t20, t22, t22a, t24, t28, t30, t32 290219 21 figure 48. ca and breq input timing 290219 22 figure 49. int/int output timing 290219 23 figure 50. hold/hlda timings 290219 24 figure 51. input setup and hold time 70
82596dx/sx 290219 25 figure 52. output valid delay timing 290219 26 figure 53. output float delay timing 290219 27 figure 54. port setup and hold time 71
82596dx/sx 290219 28 figure 55. reset input timing serial a.c. timing characteristics 290219 29 figure 56. serial input clock timing 290219 30 figure 57. transmit data waveforms 72
82596dx/sx 290219 31 figure 58. transmit data waveforms 290219 32 figure 59. receive data waveforms (nrz) 290219 33 figure 60. receive data waveforms (crs) 73
82596dx/sx outline diagrams 132 lead ceramic pin grid array package intel type a 290219 36 family: ceramic pin grid array package symbol millimeters inches min max notes min max notes a 3.56 4.57 0.140 0.180 a 1 0.76 1.27 solid lid 0.030 0.050 solid lid a 2 2.67 3.43 solid lid 0.105 0.135 solid lid a 3 1.14 1.40 0.045 0.055 b 0.43 0.51 0.017 0.020 d 36.45 37.21 1.435 1.465 d 1 32.89 33.15 1.295 1.305 e 1 2.29 2.79 0.090 0.110 l 2.54 3.30 0.100 0.130 n 132 132 s 1 1.27 2.54 0.050 0.100 issue iws 10/12/88 74
82596dx/sx intel case outline drawings plastic quad flat pack (pqfp) 0.025 inch (0.635mm) pitch symbol description min max min max min max min max min max min max n leadcount 68 84 100 132 164 196 a package height 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 a1 standoff 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 d, e terminal dimension 0.675 0.685 0.775 0.785 0.875 0.885 1.075 1.085 1.275 1.285 1.475 1.485 d1, e1 package body 0.547 0.553 0.647 0.653 0.747 0.753 0.947 0.953 1.147 1.153 1.347 1.353 d2, e2 bumper distance 0.697 0.703 0.797 0.803 0.897 0.903 1.097 1.103 1.297 1.303 1.497 1.503 d3, e3 lead dimension 0.400 ref 0.500 ref 0.600 ref 0.800 ref 1.000 ref 1.200 ref d4, e4 foot radius location 0.623 0.637 0.723 0.737 0.823 0.837 1.023 1.037 1.223 1.237 1.423 1.437 l1 foot length 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 issue iws preliminary 12/12/88 inch symbol description min max min max min max min max min max min max n leadcount 68 84 100 132 164 196 a package height 4.06 4.32 4.06 4.32 4.06 4.32 4.06 4.32 4.06 4.32 4.06 4.32 a1 standoff 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 d, e terminal dimension 17.15 17.40 19.69 19.94 22.23 22.48 27.31 27.56 32.39 32.64 37.47 37.72 d1, e1 package body 13.89 14.05 16.43 16.59 18.97 19.13 24.05 24.21 29.13 29.29 34.21 34.37 d2, e2 bumper distance 17.70 17.85 20.24 20.39 22.78 22.93 27.86 28.01 32.94 33.09 38.02 38.18 d3, e3 lead dimension 10.16 ref 12.70 ref 15.24 ref 20.32 ref 25.40 ref 30.48 ref d4, e4 foot radius location 15.82 16.17 18.36 18.71 21.25 21.25 25.89 26.33 31.06 31.41 36.14 36.49 l1 foot length 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 issue iws preliminary 12/12/88 mm 75
82596dx/sx mm (inch) 290219 37 figure 61. principal dimensions and datums mm (inch) 290219 38 figure 62. molded details mm (inch) 290219 39 figure 63. terminal details 76
82596dx/sx 290219 40 mm (inch) detail j detail l figure 64. typical lead 290219 41 mm (inch) figure 65. detail m revision summary the following represents the key differences be- tween version -005 and version -006 of the 82596ca data sheet. 1. a description of the 82596dx/sx c-stepping en- hancements was added and the 82596dx/sx b-step information was removed. 2. recommendation to use only one type of buffer (either simplified or flexible) in any given linked list. 3. added detailed description regarding operation of rcvcdt counter. 4. added new enhanced big endian mode section. the new enhanced big endian mode applies only to the 82596 c-stepping. 5. added programming recommendations regarding ru and cu start commands. these warn against starting the cu while it is active and starting the ru while it is ready. 6. emphasized that the tdr command is a static command and should not be used in an active network. 7. improved 82596dx/sx c-step timings were add- ed for all speeds. 77

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